<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform</title><link>/cadence_blogs_8/b/corporate-news/posts/guc-tapes-out-complex-3d-stacked-die-design-on-advanced-finfet-node-using-cadence-integrity-3d-ic-platform</link><description>Global Unichip Corporation (GUC), a leading global ASIC provider, has successfully taped out a complex 3D stacked die design on an advanced FinFET node process. The design, which involves a memory-on-logic configuration achieved with a wafer-on-wafer</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>