<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes</title><link>/cadence_blogs_8/b/corporate-news/posts/how-cadence-and-tsmc-are-accelerating-ai-silicon-design-at-advanced-nodes</link><description>Designing AI silicon for increasing AI/HPC workloads at advanced nodes has become one of the toughest challenges in the semiconductor industry. Escalating goal-driven PPA, reliability, and productivity-optimization demands are converging as developme</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>