<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Accelerate Chip Design with Arm Architecture: Cadence EDA Tools on AWS Graviton</title><link>/cadence_blogs_8/b/corporate-news/posts/accelerate-chip-design-with-arm-architecture-cadence-eda-tools-on-aws-graviton</link><description>Cadence has qualified its full EDA flow on Arm-based AWS Graviton CPUs, and Annapurna Labs is already using the digital implementation and signoff portion in production. 

The semiconductor industry is entering a new phase, defined by AI-scale comple</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator></channel></rss>