<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Cadence EDA Workflows Extend to Microsoft Azure Cobalt 200</title><link>/cadence_blogs_8/b/corporate-news/posts/cadence-eda-workflows-extend-to-microsoft-azure-cobalt-200</link><description>As chip designs become more complex, design and verification workloads are becoming increasingly compute-intensive. The rise of AI-driven and agentic workflows adds another dimension, with more automated and iterative tasks increasing the need for f.</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator></channel></rss>