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The miniaturization trend in electronic devices and the rise in smart and IoT device segments make adopting heterogeneous integration of chip components or 3D-ICs a viable option for miniaturization and better interconnection. This vertical stacking of ICs enables the next generation of sophisticated, intelligent devices, necessitating high chip density and terabytes of bandwidth. As per the forecast, by 2026, 28% of the world's semiconductors sold will be some form of 3D-IC, the prevalent form of which is chiplets on an interposer.
A 3D-IC with silicon interposer has the advantages of high performance, low power, increased functionality, and smaller form factor. However, in the absence of standard definitions, the supply chain ecosystem is still evolving, and so are the design, analysis, verification, and testing processes. 3D-IC needs better architectural, chiplet-to-chiplet thermal, signal, power, and electromagnetic interference (EMI) analysis than the single-process node in single-die chips, considering its multiple dimensions.
The vertical stacking of the chips calls for a cubic millimeter analysis of its product definition during the initial planning phase and enhanced capabilities for cross-die placement, timing, test, and verification. Also, streamlining the integration process flow lessens the 3D-IC design challenges and reduces time to market. Respinning silicon, even a silicon interposer, is much more expensive than respinning a PCB. Surveys show that each respin can cost around $25 million, which can vary greatly depending on the system’s complexity. With increasing complexity and coupling, you need EDA tools that have emerged around these challenges. These tools must address the challenges primarily in speed and capacity to disentangle the chip complexity.
Multi-stacking of ICs necessitates a data flow between chips via interposers. The high-frequency switching currents, intricate power delivery paths, and high parasitic couplings result in electromagnetic interference between stacked dies, making the interposers susceptible to crosstalk and power noise. All of this requires an end-to-end integrated solution, making it critical to have end-to-end high-fidelity simulation and modeling tools to analyze, design, and verify the signal, power, and thermal integrity of the complex designs and integration.
Our multiphysics analysis group builds system analysis solutions that provide highly precise electromagnetic extraction and simulation analysis, ensuring that your system works under wide-ranging operating conditions. Our intelligent 3D-aware tools with unique automation capabilities leverage the strengths of our easy-to-use two-step workflow to disentangle 3D-IC chip design complexity and support co-development and co-design environments. This provides end-to-end integration from design to fabrication signoff and predicts downstream physical effects during the design exploration phase. Our interconnect analysis and design platform decreases the product development process by 30%, accelerating the development pace. Our tools eliminate the risky manual translation of ECAD data to third-party simulation tools, reducing the design flow schedule by three to four weeks. The legacy point tools require many changes to support the end-to-end design process.
Cadence’s Clarity 3D Solver is designed to tackle EM challenges when designing complex 3D structures on chips, interposers, packages, PCBs, connectors, and cables, providing near-field finite element method (FEM) EM analysis 3D extraction, modeling, and EM simulation. It is equipped with distributed processing using a state-of-art domain decomposition algorithm. It supports simulating even immense structures on multiple 32G machines compared to the numerous terabyte machines needed for legacy 3D solvers. Our use cases demonstrated reducing simulation time from three days to 15 hours and can eliminate almost two months from the product development process.
An interposer, the critical element in 3D-ICs, lessens the power needed for routing between the dies. Low power can be achieved only by reducing the noise margin, making EM analysis essential for interposer designs. Generating mesh for analysis using legacy technologies is highly challenging, especially for ultra-thin (<1um) metal layers, as the Z-direction meshes are not easy to model using legacy algorithms. With 3D-IC-aware tools and an innovative algorithm, our Cadence team, using Clarity 3D Solver, demonstrated a realistic generation of mesh for ultra-thin layers of metals for a redistribution layer (RDL) with a thickness of less than 1um. The design comprises two modules consisting of 96 pairs of high-frequency signals per module.
The breakthrough technology of massively parallelized matrix solver helps Clarity 3D solver to achieve near-linear scalability without any accuracy loss. Elastic compute architecture enables auto partitioning, unbounded scalability, and the ability to run on any capacity machines. Cloud-optimizing distribution prioritizes lower costs, fault-tolerant restart, and dynamic deployment. Initial mesh and adaptive meshing are performed on one single machine in legacy systems, where adaptive meshing becomes a performance bottleneck. With Clarity 3D Solver, meshing (initial and adaptive) and frequency sweeping are distributed on multiple machines, making it possible to simulate immense structures on multiple 32G machines compared to multiple terabytes machines needed for legacy systems. There’s a lot of time and cost to be saved using Cadence technology.
As the technology node drops to new lower numbers, design and integration complexity climb to new heights, necessitating the demand for advanced automated solutions to handle increased complexity and techniques. Any variation can impact the performance of the silicon, which calls for extensive research, including numerous complex extractions and simulations. The limitations of legacy field solvers compel the users to simplify or partition the 3D structures into smaller segments, creating the risk of inaccuracies in the output due to artificial effects from the superficial model boundaries. The Clarity 3D Solver can address complex EM challenges when designing systems for today’s intelligent devices and can efficiently and effectively handle large and complex structures. It is the ideal solution to simulate 3D-IC structures accurately and efficiently and reduce respins and time to market. Cadence is uniquely positioned to support the 3D-IC era with its one-stop shop offering 3D design planning, implementation, and system analysis in a unified cockpit.