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It's never fun, finding problems in your design—especially when you find them late in your design cycle. That was the frustration that ams faced, until the company integrated an electrically aware design flow into its process about six months ago.
ams was one of about 50 Cadence customers who shared their experiences, lessons learned, and best practices at the Cadence Theater at this year’s Design Automation Conference (DAC) in San Francisco. Most of these presentations are now available online for viewing.
Headquartered in Austria, ams develops and manufactures high-performance analog semiconductors. “We do the ‘tough stuff,’” as Thomas Mörth, director of engineering for the company’s foundry division, noted in his DAC talk.
ams’s previous design flow consisted of fairly standard schematic entry, simulation, and a mix of schematic-driven layout as well as polygon-pushing layout. When schematic-driven layout was used, then there would be steps for DRC/LVS, parasitic extraction, signoff simulation, and signoff analysis.
The problem with this traditional flow was that problems were found very late in the process, said Mörth. This was costly in terms of time and effort. For example, problems detected during DRC/LVS meant that the engineers would have to go back to the layout entry to resolve the issues. Similarly, problems found in layout meant a return to the schematic step. Sometimes, the team would have to recreate the whole layout. Another key issue here, according to Mörth, was the loose coupling between the front end and the back end, with information often shared between schematic and layout engineers via emails and notes.
To solve these problems, ams turned to an electrically aware design flow from Cadence, based on the Cadence Virtuoso Layout Suite for Electrically Aware Design. “This is a way to find problems with electromigration and with parasitics way earlier in the flow,” said Mörth.
How did ams change its design flow? “There’s a dataset you have to create in order to make the layout tool aware of what you want to do. Then in the layout step, EAD enables you to do on-the-fly parasitic extraction and also on-the-fly electromigration checks,” explained Mörth. “When you do parasitic extraction during layout creation—and this can be done on a partially finished layout—the final parasitic extraction can be considered final because, most likely, the problems found have already been fixed in the intermediate iterations that you do when you create your layout. So you have final parasitic extraction and then signoff simulation.”
He continued, “With the electrically aware design flow, the design cycle is shortened a lot. And of course, you can do electromigration checks and parasitic extraction on the fly, which helps you find problems in these (areas) earlier in the design process.”
ams followed these key steps to set up its electrically aware design flow:
After simulation, the team selected the electrically aware design result view from the Virtuoso tool and created the data set for the layout tool. All currents simulated on individual nets are stored in a constraints database for the layout tool.
For electromigration analysis, the engineers could then open the browser for Virtuoso Layout Suite for Electrically Aware Design, load the settings for the tool, load the dataset just created with simulation, perform the electromigration check, and get the results. Mörth noted that for every net here, you get a traffic guide that tells you if you are within the specification of the maximum current for that net, near the spec, or are way off. You can then fix the violations in the layout tool.
Mörth concluded his talk by highlighting some key take-aways from ams’s experience with its Cadence electrically aware design flow:
See ams’s slides and hear Mörth’s talk from the archived proceedings. Look for Session #25 from Tuesday, June 9. You won’t need to register to access the recording.