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As Cadence celebrates 25 years of its Virtuoso Analog Design Environment (ADE), the company has also announced its next-generation platform, which promises an average of 10X performance and capacity improvement. There are new technologies within Virtuoso ADE and enhancements to Cadence Virtuoso Layout Suite to address requirements for automotive safety, medical device, and Internet of Things (IoT) applications.
I thought this would be a fine time to look back at a few capabilities under the Virtuoso umbrella to see how design challenges have evolved and anticipate what might come next.
Electrically Aware Design
David White, a Cadence Distinguished Engineer, leads an R&D team that works on Virtuoso Layout Suite for Electrically Aware Design, which represents the industry’s first electrically aware, in-design solution for custom ICs. He reflected on recent history, when designers would do their schematic design, simulate, make sure the design meets intent, and then hand the design over to the layout team for P&R to complete the physical design—without knowledge of the electrical impact of their work.
“There was a lot of ‘rip up and reroute,’ White noted. "We spoke to customers when we began developing our tool and they’d talk about spending 25 to 30% of their time going through a number of layout cycles to fix parasitic-based problems. With so many cycles, some would hit scheduling limits and then have to create overly conservative layouts to overcome the issues, trading productivity for performance."
With Virtuoso Layout Suite for Electrically Aware Design, layout engineers and designers gain visibility into the physical design process and can ensure that design intent is met all the way through layout. They can check a layout as it is being created, identify and fix any electromigration problems, and re-simulate the layout as needed to verify that it is electrically correct. Even though the tool operates in real time, customers still have an expectation on accuracy. The tool’s qualification results are typically within +/- 5% for 95% of the foundry test patterns, which is basically signoff accuracy in-design. The team continues to explore schematic-driven solutions for collaborative verification with layout, along with more automation for electrically correct routing.
Visualization and Analysis
Iain Farquharson, a sr. software architect at Cadence, works on the Virtuoso Visualization and Analysis tool, which provides statistical analysis of yield optimization from display digital signals to analog to RF and everything in between. Now a third-generation waveform tool, the original version was written in SKILL, Farquharson recalls. Engineers liked the original tool’s flexibility and it was fast enough for the simulators of the time. In fact, Farquharson remembers when the team had the Virtuoso tool working on Windows at one point (!).
Today, the preponderance of very large single-design datasets is making a big impact. “We have terabytes of data coming off the simulator that needs to be analyzed and displayed in a reasonable amount of time—minutes and seconds, instead of hours and minutes. We’re good at displaying this accurately—our tool can do one billion data points interactively,” said Farquharson. “So much more is shifting to the statistical side of analysis.”
White notes that big data and analytics have also influenced the evolution of Virtuoso Layout Suite for Electrically Aware Design. He and his team have tapped into machine-learning algorithms to deliver speed and accuracy. “Our data is very transient and is produced by physical elements that are non-linear in nature. So you can’t just look at a static set of data and determine its impact. Customers are overwhelmed with data and need analysis in near real time. Our tool can aggregate data, extract relevant information, and identify where and how to fix the problem.”
Visualization, White continued, is the best way to present a large amount of data. That’s why the work from Farquharson’s team touches the rest of the Virtuoso team.
Paul Foster is a software architect on the Virtuoso ADE team. He helps develop various capabilities within the environment, such as integrated design characterization and modeling, analog/mixed-signal design and model validation, and schematic model generator. While the design characterization and modeling feature provides high-level abstraction with big blocks, the schematic model generator breaks it all down into a “Lego-based flow,” with a frequency generator, input voltage sampler, counter, and divider, said Foster. All of this is controlled on the schematic, and there’s a library of 200 building blocks from which designers can select what they’d like to place on the schematic and then hit a button to create a model using Virtuoso ADE.
From Foster’s standpoint, one of the biggest changes in customer design challenges is the need for a higher level of abstraction. “As designs get more and more complex and overall bigger, now they need to move to real number representation. The other thing we’re seeing is the need for performance and retaining some level of electrical accuracy.”
Designers are also demanding more automation, toolboxes, and configurable verification IP. “A designer never wants to sit down with a blank piece of paper,” said Foster. “We’re moving toward more top-down mixed-signal design flow, taking requirements and abstracting them into a simulate-able spec, implementing the transistor level, verifying the implementation to a simulate-able spec, then moving to layout and extraction.”
Get more details—including a fun video—about the 25th anniversary of Virtuoso technology here. From this page, you can also learn how you can get a chance to win a Beats solo2 wireless headphone by sharing your Virtuoso story.