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It’s a huge conundrum: as process nodes shrink, design times grow longer, while project schedules remain the same or get reduced. Growing the design team isn’t always an option.

“There are not enough human beings in North America who know how to do layout to finish your design project on time and on budget,” said Rob Rutenbar, head of the Department of Computer Science and Abel Bliss Professor of Engineering at the University of Illinois. “We hope there’s a better approach.”

Rutenbar moderated a Cadence-sponsored lunch panel, “5 Ways to Boost Your Productivity Designing Custom with Advanced Nodes,” during the Design Automation Conference in Austin. Panelists included:

• Roman A. Guzman, a mask designer at AMD
• Jeff Johnson, a design engineering director at Cadence
• Jayanta Lahiri, VP of engineering for the physical IP group at ARM
• Tom Quan, a director at TSMC who runs the company's Open Innovation Platform marketing programs

Kicking off the June discussion, Rutenbar noted that there are two types of electronic design automation (EDA) tools: insurance and pain relief. “Advanced nodes require both varieties,” he said, noting that there are some tasks so horrible that no one wants to do them by hand and there are other tasks that are so difficult that you’d be willing to try different methods of insurance.

We’re now at a pivot point where it’s time to start thinking about new ways to do things, said Rutenbar.

Design Challenges Abound

Johnson highlighted that the growing complexity in rules, layers, and all of their requirements is making the layout designer’s job particularly difficult. As much as a designer studies the Design Rule Manual (DRM) and runs design rule checks (DRCs), about half the time it’s still hard to determine what’s really wrong.

Variation continues to be a challenge, noted Lahiri, who expects to see improvements in process variation tools to enable simultaneous power and timing closure. Quan highlighted a variety of concerns: device self-heating, layout-dependent effects, EMIR, gradient densities. How, he asked, can we address these issues early so designers don’t have to wait until the end of the flow to discover problems?

The FinFET process presents some new challenges for custom designers. “FinFETs have a lot of benefits—high drain currents, low leakage,” noted Quan. “But with the 3D structure of FinFETs, you have to model them accurately. There’s a lot more capacitance, EM because of high current capability, and more pronounced layout-dependent effects.”

Lahiri noted that FinFETS have, indeed, given ARM a platform for lower voltage. The challenge, he said, is that designers also want high speed. The number of process, voltage, and temperature (PVT) corners is enormous in these designs, burning a lot of disk space and CPUs. He noted that ARM works with EDA partners and there’s been some improvement, “but, still, we have miles to go.” He also added that modeling is quite difficult. After layout, engineers need to extract and do a simulation run and create a view that can be used by the SoC designer.

Solutions On the Way

So, what kinds of tools and methodologies are needed to address these challenges?

For Guzman, who’s in the trenches each day working through various design challenges, physical verification is an area ripe for improvement as he continues to learn new rules and layers. Early in a process, in particular, the tedious tests for verification consume the bulk of his time, as does addressing electromigration and IR-drop (EMIR). “As a layout designer, automation tools like routers can save time. Anything automated, interactive, or on-the-fly type stuff that can save hours” is valuable, Guzman said.

In Johnson’s view, methodology is key. “Right now, permutations and computation of rules keep going higher, but you can in some cases artificially limit those things,” he said. “Once you start to simplify the problem, it makes it go easier and quicker and leads very well to more automation and placement and routing tools. As process gets more complicated, we want to develop methodologies to make it simpler for people to use.”

Quan noted that his goal is to continue working closely with Cadence and key EDA and IP partners early in the development cycle to solve the challenges. Tool certification is important, as is aggregating the tools in an integrated tool certification flow. By anticipating and addressing challenges as they emerge, designers using the certified tools can productively migrate to advanced nodes with confidence.

Opportunities to Increase Productivity

Rutenbar wrapped up the panel discussion with a few key takeaways. First off, there’s broad opportunity to increase productivity via new methodologies, up-front planning, and through more automation. There are also opportunities for in-design verification and analysis. Finally, more intelligent simulation environments can be a huge benefit.

Christine Young