The Design Chronicles Blogs

What kinds of techniques are you employing to address physical and electrical challenges at advanced nodes?

At 10nm and beyond, you’ll need to start addressing coloring. When you get to 7nm, color-aware cell placement, metal cutting rules, and density control will be critical. Plus, FinFET design complexity isn’t only about routing, there’s an impact on the entire flow:

• The actual transistor has new characteristics that need new SPICE models. The resulting high drive presents a lot of energy down the wire, so electromigration becomes a big concern.
• The actual design itself will be bigger, with bigger blocks, so you’ll need tools that support large designs. The increase in design rules can create runtime challenges for EDA flows.
• Triple patterning will be in play on the lithography side.
• Parasitic variation is another problem. With high-resistance wires and layer stacks that promise to be quite varied, optimization engines will need to understand layer selection, and buffering must be linked together.

Rod Metcalfe, group director of digital implementation at Cadence, outlined these challenges during his June 7 talk at the TSMC booth at this year's Design Automation Conference (DAC). This background paved the way for his discussion of Cadence’s long collaboration with TSMC on FinFET design. Cadence’s digital as well as signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET process. TSMC certification covers various aspects of the design flow, including accuracy, functionality, and quality of results.

 Cadence’s toolsuite for FinFET design covers:

• Library characterization
• IP integration
• Digital signoff
• Full custom layout
• Mixed-signal design
• Digital implementation

Focusing on the digital implementation side, Metcalfe noted that FinFET requirements start from initial placement. There are many new constraints that address FinFET transistors and double-/triple-pattern routing, from implant layer checking to avoid spacing errors to horizontal and vertical standard-cell placement checks. Regarding routing requirements, the latest TSMC FinFET process calls for the router to support TRIM metal, which reduces end-of-line spacing, minimizes area, and improves routing density. At signoff, accuracy is critical, and you don’t want to build in pessimism. Each of these FinFET requirements are supported by tools in Cadence’s full-flow digital design solution, which supports the current 7nm DRM.

Christine Young