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What kinds of techniques are you employing to address physical and electrical challenges at advanced nodes?
At 10nm and beyond, you’ll need to start addressing coloring. When you get to 7nm, color-aware cell placement, metal cutting rules, and density control will be critical. Plus, FinFET design complexity isn’t only about routing, there’s an impact on the entire flow:
Rod Metcalfe, group director of digital implementation at Cadence, outlined these challenges during his June 7 talk at the TSMC booth at this year's Design Automation Conference (DAC). This background paved the way for his discussion of Cadence’s long collaboration with TSMC on FinFET design. Cadence’s digital as well as signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET process. TSMC certification covers various aspects of the design flow, including accuracy, functionality, and quality of results.
Cadence’s toolsuite for FinFET design covers:
Focusing on the digital implementation side, Metcalfe noted that FinFET requirements start from initial placement. There are many new constraints that address FinFET transistors and double-/triple-pattern routing, from implant layer checking to avoid spacing errors to horizontal and vertical standard-cell placement checks. Regarding routing requirements, the latest TSMC FinFET process calls for the router to support TRIM metal, which reduces end-of-line spacing, minimizes area, and improves routing density. At signoff, accuracy is critical, and you don’t want to build in pessimism. Each of these FinFET requirements are supported by tools in Cadence’s full-flow digital design solution, which supports the current 7nm DRM.