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At the Design Automation Conference in June, I stopped by Cadence’s booth for a demo of our RocketSim parallel simulation engine. (Cadence acquired Rocketick, who developed the tool, back in April.) Dave Lidrbauch, sr. principal product manager, led the way.
First, a little history. Initially, there were Verilog interpreted-code simulators such as Verilog-XL, then came the second-generation compiled-code simulators, like Cadence’s Incisive platform. Many companies have been working on accelerating the logic design side of simulation engines. But in terms of speed, improvements haven’t kept pace with the rate at which design sizes are growing, Lidrbauch explained.
It’s been a tough challenge because parallelizing simulation involves a variety of factors:
The engineers behind the RocketSim engine figured out a unique way to strip out the pieces and identify independent threads of execution that can be parallelized. Lidrbauch explained that the tool goes down to the language level and determines the dependencies among those threads. Originally, the developers targeted GPUs, which requires a fine-grain approach. Through this process, they also learned about the limitations of GPUs in terms of latency and their lack of flexibility to scale up with cloud resources. So in the end, they realized they needed to exclusively target standard x86 processors.
The RocketSim engine divides up the simulation that runs on compiled-code simulators, such as the Incisive environment, into accelerate-able and non-accelerate-able portions, and places the parts that can be accelerated, such as the gate-level or SystemVerilog portion, on a multi-core thread. There’s no need to change the testbench, the design, or the assertions. The engine is accessible directly from the Incisive platform and the two tools talk to each other when needed.
Using this technology, you can determine where your design’s event density lies—mostly on the design side, on the testbench side, or shared across the two. The engine has demonstrated the ability to accelerate simulation from 2X-30X, depending on the design. It works on large and complex jobs, with more than one billion logic gates. It’s also future-proof—since the work happens at the language level, the tool isn’t dependent on node or whether your design is a CPU, processing, or datapath design, nor does it care about the hierarchy of the design. When you’re ready to simulate, you can either tell the RocketSim engine how many cores you want to use, or have the tool decide. You won’t have to recompile or repartition to use a different mix of core resources.
Lidrbauch calls the RocketSim engine the third generation of simulation engine. Whether you’re saving days or weeks, the marriage of the Incisive and RocketSim technologies is a fortuitous one, given how large and complex designs are becoming.