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With a portfolio including dedicated automotive ICs, discrete and power transistors, MEMs and specialized imaging sensors, and digital ASICs, STMicroelectonics is a leading provider of smart driving and internet of things (IoT) technologies. On June 7, Pierluigi Daglio, analog verification manager at the company, took the stage at the Cadence Theater at the Design Automation Conference (DAC) to share how an electrically aware design flow can shorten the design cycle.
In the mid-80s, STMicroelectronics introduced its BCD technologies, integrating bipolar, CMOS, and DMOS into a single-process platform for power ICs. The technologies are widely used today, and include:
Designing these and other chips with a traditional design flow comes with limitations. It’s a serial process, for one, and the design must also accept tradeoffs, Daglio said. There are no notions of the electrical information inside the layout. In addition, he noted, LVS clean is a must in order to perform parasitic extraction.
Bringing into simulation electrically aware design after circuit/schematic design, on the other hand, allows you to find and fix problems early on. “You save a lot of time in your design phase,” Daglio said.
Electrically aware design enables these flows:
Earlier this month, STMicroelectronics announced that it is using Cadence’s next-generation Virtuoso platform to enhance layout design automation for its BCD SmartPower technologies. The platform includes an electrically aware design capability via the Virtuoso Layout Suite for Electrically Aware Design. At the top level, Daglio explained, the flow allows designers to set resistance constraints, perform point-to-point resistance calculation, and do electromigration (EM) checks with a custom approach. His team is working with Cadence to implement DC IR-drop constraints in the schematic. In addition, STMicroelectronics has updated its design kits to support the newest Virtuoso platform in production use.
At the cell level, the Virtuoso flow is useful for the in-design phase, providing features like EM analysis based on dynamic transistor-level simulation, point-to-point resistance calculation, RCC parasitic extraction, and schematic electrical constraints. “Electrically aware design prevents most of the EM issues in the layout generation phase, increasing the productivity of the designer and speeding up the whole IC verification process,” said Daglio.
He noted that while electrically aware design shouldn’t replace your signoff tool, it does help prevent large problems from cropping up at the end of the design cycle. And, he said, it is fairly easy to integrate into the flow.