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The automotive industry has traveled a long and interesting road, from the Ford Model T in 1915 to today’s prototypical self-driving cars. Vehicles now commonly have hundreds of electronic components, with applications such as infotainment and advanced driver assistance systems (ADAS) driving the demand for more in-car electronic control units (ECUs).
Charles Qi, a senior design engineering architect at Cadence, will discuss automotive design challenges and IP solutions at TSMC Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara. Titled “Building Silicon IP and Subsystems for Automotive Infotainment and ADAS Applications,” Qi’s talk in the forum’s IP Track will take place at 5:00pm on Thursday, September 17 (2015).
I chatted with Charles before the show for a preview of his talk. Read on, and be sure to attend his Thursday session for a deeper dive.
What are some of the key ADAS applications that are demanding a high-performance, flexible compute platform?
There are three main areas: audio and sound, radar, and vision. In the area of audio and sound, there are functions such as rear object detection, cabin noise reduction, and emergency recognition. Front collision avoidance braking, adaptive cruise control, and rear collision detection are some examples of radar applications. And there are quite a lot of vision applications: driver monitoring, lane detection, rain and fog detection, and pedestrian detection, to name a few.
Let’s talk about how IP can support automotive designs. On the processor side, how can Cadence’s Xtensa processors and Tensilica DSPs meet automotive application requirements?
With the Xtensa Processor Generator, engineers can quickly build their own task-specific processor for their application. Xtensa processors can scale up in performance, offer flexibility, and feature an architecture that supports fully automated hardware and software tool generation, so design teams can get creative using the tools.
Tensilica DSPs, built on the Xtensa base, can meet ADAS computational demands. These DSPs are designed for high performance, with their VLIW and 64-way SIMD architectures, and for low power, operating at 70mW to less than 300mW. And, they’re about a quarter of the size of a GPU.
What is the trend now with networking technologies in automotive designs?
Networking technologies are not new for automotive electrical/electronic (E/E) architectures. Traditionally, automotive designers have used low-data-rate control solutions like LIN and CAN, or they’ve used high-cost, proprietary solutions like MOST and FPD-Link.
We’re really now seeing how Ethernet technology can streamline the automotive architecture. It is low cost, provides bandwidth that scales up to 400Gbps, is backed by a large ecosystem, and also features standardization in terms of time synchronization, QoS and latency guarantee, redundancy, VLAN isolation, and power efficiency.
Memory bandwidth demands are increasing for vehicles. What makes LPDDR suitable for automotive designs?
LPDDR4 provides the memory bandwidth needed at cost, power, and reliability levels that automotive engineers want. It offers twice the performance of LPDDR3, 40% lower power than DDR4, and better signal integrity/EMI characteristics than previous-generation DDR technologies. It also features extended operating range and temperature compensation.
Along with using IP, what is an approach that automotive designers can adopt to further shorten their design cycle?
An IP subsystem with pre-validated components can speed up hardware/software integration and also help enhance quality and reliability. Designers can save time and effort in verifying individual components, and be assured that the components will work well together. (See Figure 1 for a depiction of an IP subsystem.)
Figure 1: An IP subsystem with pre-validated components can reduce time to market.
What about functional safety and device reliability?
Functional safety and reliability are at the heart of automotive E/E design. Functional safety is primarily guided by the ISO 26262 standard. ISO 26262 achieves functional safety at the system level through vigorous quality management through the entire product lifecycle, including product specification, architecture, implementation, and testing. Device reliability is primarily governed by silicon testing according to AEC-Q100. Even though an IP cannot be directly certified for ISO 26262 or AEC-Q100, the requirements trickle down to the IP level. Cadence is working closely with customers to proactively address these requirements.