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Digital Designers Discuss Ways to Close the Power Gap for Wearable Devices

By Christine Young | 4 Dec 2015

How often do you have to charge your electronic devices? What is often an annoying problem for consumers is an even more vexing challenge for the engineers who design wearable devices. A panel of engineers explored ways to close the power gap for wearable...

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wearables | broadcom | Qualcomm | front end design | Texas Instruments | power
Q&A: Love of Math Adds Up to Passion for Formal Verification

By Christine Young | 30 Nov 2015

Exhaustive and comparatively efficient, formal verification is a powerful option to other verification methods because it can detect bugs much earlier in the design cycle. Anyone with a love for math, like John Havlicek, can understand the unique advantages...

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SystemVerilog | math | assertions | DDR IP | Formal verification
Q&A: Clearing the Obstacles to Electrical Signoff

By Christine Young | 23 Nov 2015

One of Alessandra Nardi’s favorite quotes is, “You can’t direct the wind, but you can adjust the sails.” An R&D group director on Cadence’s electrical signoff team, Nardi is inspired by the philosophy behind this German proverb. Nardi, who has a PhD in...

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Design Chronicles | electrical signoff | power integrity | Timing analysis | signoff
ARM and Cadence on Miniaturizing Sensing and Power for IoT Design

By Christine Young | 16 Nov 2015

Designing connected devices comes with the added challenges of small form factor and long battery life requirements. SoCs integrating the processor, radio, and sensors provide an answer, as does MEMS technology, which miniaturizes sensing and energy harvesting...

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ARM Techcon | IoT | sensors | miniaturization | Coventor | ARM | MEMS
ARM's Simon Segars Promotes Trust, Security, and Privacy for Our Connected World

By Christine Young | 13 Nov 2015

“Learn how to see. Realize that everything connects to everything else.” – Leonardo da Vinci Everything connects to everything else – this idea remains as true today as it did back in da Vinci’s day. Especially when it comes to the...

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security | Simon Segars | IoT | Symantec | Internet of Things | ARM | Progressive Insurance
Tracking Progress on Formal Testbenches at ARM Austin

By Christine Young | 9 Nov 2015

Need to make a case for using formal in your organization? ARM’s Austin team now has two years under its belt using formal verification. Vikram Khosa, a staff design engineer on the team, has a few tips and tricks to share from the experience so far....

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verification engineers | formal testbenches | ARM | Formal verification
Driving Automotive Vision Applications with the Right DSP

By Christine Young | 2 Nov 2015

We’re not yet riding in driverless cars, yet today’s vehicles are doing more for us than perhaps Henry Ford could have imagined. From pedestrian detection to driver monitoring, parking assistance and infotainment systems, these features are making our...

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automotive vision | DSP | Design Chronicles | vision processing | Computer Vision | Tensilica | vision computing | image processing
Berkeley Professor Pushes Agile Methodologies for More Efficient Chip Design

By Christine Young | 28 Oct 2015

Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not? “Twenty years ago, technology people had fun making fun of ITRS predictions,” said...

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Berkeley engineering | AMS | agile software development | open source | mixed signal | UC Berkeley
Imagination Dispels 10 Myths About Formal Verification

By Christine Young | 26 Oct 2015

Do you think that you need to have a PhD in order to use formal verification? Do you believe that formal is difficult because you need specifications? Are you concerned that formal doesn’t scale? These are just a few of the formal verification...

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DAC | formal | Imagination | Formal verification
Q&A: John Lupienski on How Mobile and IoT Designs are Driving IP Requirements

By Christine Young | 19 Oct 2015

John Lupienski III is a product engineering director at Cadence, where he leads a team that, as the primary technical support interface to the company’s PHY IP R&D group, supports customers in their implementation of high-speed interfaces. John has a...

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IP | IoT | mobile | high speed interfaces
Q&A: Software Architect Zhuo Li on Exoplanets, Cybersecurity, and Other Engineering Frontiers

By Christine Young | 12 Oct 2015

Zhuo Li is a software architect who works on Cadence’s advanced digital implementation flow, namely the Innovus Implementation System and the Genus Synthesis Solution. A recipient of the IEEE Council on Electronic Design Automation (CEDA) Early Career...

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NAS | NAE | science | US Frontiers of Engineering | cybersecurity
Broadcom Design and Verification Engineer: "My First 100 Days in Formal Land"

By Christine Young | 9 Oct 2015

Jasper User Group 2015, held Oct. 7-8 at Cadence’s San Jose headquarters, brought together top formal verification experts and enthusiasts to share best practices and lessons learned. One such enthusiast was Alex Orr, principal engineer for IC design...

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Jasper User Group | configurable IP | broadcom | assertions | signoff | Formal verification
Q&A: Drones, Robots, and the New Tensilica Imaging/Vision DSP

By Christine Young | 8 Oct 2015

Image and vision processing require a tremendous amount of processing power, not to mention a large amount of memory bandwidth. And when you consider the mobile and wearable devices that utilize these functions, it’s clear why low energy consumption is...

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DSP | vision processing | IoT | Computer Vision | Tensilica | drones | image processing
TSMC OIP Ecosystem Forum: Tackling Coloring, Cell-Pin Access, and Variation at TSMC 10nm

By Christine Young | 5 Oct 2015

At 10nm, design tasks that were once optional have become mandatory. Take coloring, for example—shrinking processes have required a transition from a route-driven implementation to a color-driven one. Cadence’s Rahul Deokar addressed coloring and other...

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Extraction | P&R | TSMC OIP | PPA | Innovus | FinFET | signoff | digital design flow
TSMC OIP Ecosystem Forum: Why Collaboration Helps the Semiconductor Industry Thrive

By Christine Young | 30 Sep 2015

While the Internet of Things (IoT), mobile, and automotive markets are fueling growth in the semiconductor industry, there are still formidable challenges for engineers to address. That’s why it will take close collaboration across the design ecosystem...

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automotive | collaboration | Cliff Hou | CoWoS | Jack Sun | IoT | Avago | TSMC OIP | InFO | mobile | xilinx | Rick Cassidy | power
What's Happening at This Year's Jasper User Group Conference?

By Christine Young | 29 Sep 2015

It’s almost time for the Jasper User Group Conference, Cadence’s annual gathering about all things formal. This year’s conference is scheduled for October 7 and 8 in the Building 10 auditorium at Cadence’s San Jose headquarters. There’s still time to...

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Jasper User Group | verification engineers | JUG 2015 | Formal verification
Q&A: George Cochrane on Academia/Business Collaboration, Electronics, and the Passion of Nikola Tesla

By Christine Young | 28 Sep 2015

In 2007, Cadence launched its Academic Network to promote its technologies and methodologies at universities renowned for their engineering and design excellence. Today, the Cadence Academic Network is a robust community of universities, research institutes...

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internships | Nikola Tesla | Academic Network | Oxford
TSMC OIP Ecosystem Forum: Harnessing the Power of Collaboration

By Christine Young | 23 Sep 2015

“The most ambitious ideas come with a million moving pieces. The only way to bring it all together is through the power of collaboration.” —TSMC Indeed, that collaborative energy was out in full force throughout TSMC Open Innovation...

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automotive | collaboration | IoT | TSMC OIP | mobile | Rick Cassidy
How EDA Standards Are Born—and Why You Should Get Involved

By Christine Young | 21 Sep 2015

Fortunately, we are well beyond the contentious “standards wars” that brewed in the 1990s and 2000s, when EDA vendors took sides in various standards disputes. Today, the process for adopting a standard is much more civil and even collaborative....

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Si2 | EDA vendors | Stan Krolikoski | EDA standards | Accellera | interoperability | IEEE
Streamlining Automotive Infotainment and ADAS Designs with IP

By Christine Young | 14 Sep 2015

The automotive industry has traveled a long and interesting road, from the Ford Model T in 1915 to today’s prototypical self-driving cars. Vehicles now commonly have hundreds of electronic components, with applications such as infotainment and advanced...

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functional safety | infotainment | ECUs | TSMC | automotive electronics | automotive IP | ISO 26262 | ADAS
How You Can Simplify Flow Handoffs Between Schematic and Layout Engineers

By Christine Young | 7 Sep 2015

Looks like the schematic had some ECOs. What changed? Is the layout for this design DRC/LVS clean? Which rev of the schematic was the layout created for? Is this the correct version of the IP that should be used? Is the verification team using the...

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DAC | IP management | collaboration | mixed signal design | schematic engineer | layout engineer | design data management | ClioSoft | flow handoff
Q&A: Neeti Bhatnagar on the Growing Importance of Software-Hardware Debug

By Christine Young | 31 Aug 2015

With so much system functionality now also controlled by software versus hardware alone, it’s become more critical to debug at both the hardware and software levels. Neeti Bhatnagar, a software engineering group director at Cadence, knows this well. Neeti...

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software hardware debug | Caltech | embedded software debug | SystemC | high level synthesis | NASA JPL | women in tech | software engineering | verification
University of Toronto Prof. Farid Najm: Managing Design Challenges for Power-Constrained SoCs

By Christine Young | 24 Aug 2015

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling, meeting power integrity targets, managing voltage drop, and other related challenges. While the solutions aren’t simple, there are emerging techniques that offer some...

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constraints generation | Professor Farid Najm | power constrained SoCs | power grid | power integrity | voltage drop | power scheduling
Q&A: Anne Hughes on Memory IP Advancements and Women in Tech

By Christine Young | 20 Aug 2015

Memory is a ubiquitous component in today’s electronic devices, and advancements in the technology are resulting in higher performing, lower power memory products. Anne Hughes is a design engineering group director at Cadence, where she manages a team...

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STEM | LPDDR | JEDEC | memory IP | Denali | DDR | DDR IP | women in tech
Socionext Explains Why High-Level Synthesis Is a Winning Technology for IP Design

By Christine Young | 17 Aug 2015

Have you been weighing the pros and cons of replacing a hand-coded RTL methodology with high-level synthesis (HLS)? For Socionext, using HLS certainly yielded benefits in performance, power, and area for its advanced IP and SoC designs. A developer of...

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High-Level Synthesis | TLM | IP design | Socionext | DAC 2015 | SoC design | HLS

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