The Design Chronicles Blogs

How often do you have to charge your electronic devices? What is often an annoying problem for consumers is an even more vexing challenge for the engineers who design wearable devices. A panel of engineers explored ways to close the power gap for wearable...

Exhaustive and comparatively efficient, formal verification is a powerful option to other verification methods because it can detect bugs much earlier in the design cycle. Anyone with a love for math, like John Havlicek, can understand the unique advantages...

One of Alessandra Nardi’s favorite quotes is, “You can’t direct the wind, but you can adjust the sails.” An R&D group director on Cadence’s electrical signoff team, Nardi is inspired by the philosophy behind this German proverb. Nardi, who has a PhD in...

Designing connected devices comes with the added challenges of small form factor and long battery life requirements. SoCs integrating the processor, radio, and sensors provide an answer, as does MEMS technology, which miniaturizes sensing and energy harvesting...

“Learn how to see. Realize that everything connects to everything else.” – Leonardo da Vinci Everything connects to everything else – this idea remains as true today as it did back in da Vinci’s day. Especially when it comes to the...

Need to make a case for using formal in your organization? ARM’s Austin team now has two years under its belt using formal verification. Vikram Khosa, a staff design engineer on the team, has a few tips and tricks to share from the experience so far....

We’re not yet riding in driverless cars, yet today’s vehicles are doing more for us than perhaps Henry Ford could have imagined. From pedestrian detection to driver monitoring, parking assistance and infotainment systems, these features are making our...

Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not? “Twenty years ago, technology people had fun making fun of ITRS predictions,” said...

Do you think that you need to have a PhD in order to use formal verification? Do you believe that formal is difficult because you need specifications? Are you concerned that formal doesn’t scale? These are just a few of the formal verification...

John Lupienski III is a product engineering director at Cadence, where he leads a team that, as the primary technical support interface to the company’s PHY IP R&D group, supports customers in their implementation of high-speed interfaces. John has a...

Zhuo Li is a software architect who works on Cadence’s advanced digital implementation flow, namely the Innovus Implementation System and the Genus Synthesis Solution. A recipient of the IEEE Council on Electronic Design Automation (CEDA) Early Career...

Jasper User Group 2015, held Oct. 7-8 at Cadence’s San Jose headquarters, brought together top formal verification experts and enthusiasts to share best practices and lessons learned. One such enthusiast was Alex Orr, principal engineer for IC design...

Image and vision processing require a tremendous amount of processing power, not to mention a large amount of memory bandwidth. And when you consider the mobile and wearable devices that utilize these functions, it’s clear why low energy consumption is...

At 10nm, design tasks that were once optional have become mandatory. Take coloring, for example—shrinking processes have required a transition from a route-driven implementation to a color-driven one. Cadence’s Rahul Deokar addressed coloring and other...

While the Internet of Things (IoT), mobile, and automotive markets are fueling growth in the semiconductor industry, there are still formidable challenges for engineers to address. That’s why it will take close collaboration across the design ecosystem...

It’s almost time for the Jasper User Group Conference, Cadence’s annual gathering about all things formal. This year’s conference is scheduled for October 7 and 8 in the Building 10 auditorium at Cadence’s San Jose headquarters. There’s still time to...

In 2007, Cadence launched its Academic Network to promote its technologies and methodologies at universities renowned for their engineering and design excellence. Today, the Cadence Academic Network is a robust community of universities, research institutes...

“The most ambitious ideas come with a million moving pieces. The only way to bring it all together is through the power of collaboration.” —TSMC Indeed, that collaborative energy was out in full force throughout TSMC Open Innovation...

Fortunately, we are well beyond the contentious “standards wars” that brewed in the 1990s and 2000s, when EDA vendors took sides in various standards disputes. Today, the process for adopting a standard is much more civil and even collaborative....

The automotive industry has traveled a long and interesting road, from the Ford Model T in 1915 to today’s prototypical self-driving cars. Vehicles now commonly have hundreds of electronic components, with applications such as infotainment and advanced...

Looks like the schematic had some ECOs. What changed? Is the layout for this design DRC/LVS clean? Which rev of the schematic was the layout created for? Is this the correct version of the IP that should be used? Is the verification team using the...

With so much system functionality now also controlled by software versus hardware alone, it’s become more critical to debug at both the hardware and software levels. Neeti Bhatnagar, a software engineering group director at Cadence, knows this well. Neeti...

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling, meeting power integrity targets, managing voltage drop, and other related challenges. While the solutions aren’t simple, there are emerging techniques that offer some...

Memory is a ubiquitous component in today’s electronic devices, and advancements in the technology are resulting in higher performing, lower power memory products. Anne Hughes is a design engineering group director at Cadence, where she manages a team...

Have you been weighing the pros and cons of replacing a hand-coded RTL methodology with high-level synthesis (HLS)? For Socionext, using HLS certainly yielded benefits in performance, power, and area for its advanced IP and SoC designs. A developer of...