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The EDA Industry is the unsung hero behind for modern era electronic revolution since early 80s and gets the spotlight it deserves in the recent DAC newsletter.
I would like to applaud the author Geoffrey James, for crediting the EDA industry in rising to the challenges associated with each and every technology process node, in particular advancing the use of multi-core architectures. The EDA industry continues to help the semiconductor sector by solving some of their core business issues, such as chip performance, reliability, power consumption, manufacturability and productivity.
The demand for higher clock frequency and less power/heat dissipation is the main driving force for multi-core configuration. As an enabler, the EDA industry must stay ahead of the curve. We must invigorate parallelism, multi-tasking capability within applications while delivering an array of automation tools for design implementation, analysis and validation. We must also continuously focus on ease-of-use to enable better and faster design of multi-core systems, and enable time-to-market saving for our users. “The EDA industry has always depended upon the most-recent generation of chips to provide the power needed to crunch the data required to build the next generation” noted by Tom Spyrou, Cadence Distinguished Engineer and Encounter Platform RnD Manager, who is featured in this interview.
This challenge is immersive, and the Encounter Digital Implementation System is a great example. One of the obvious challenges is transforming enormous number of lines of code, that were not written to be parallel, to be multi-threaded, distributed or both. The solution must also be optimized for scalable performance and adhere to our customers’ unique computing environments and needs. Another challenge, which is equally important, is to speed up any serial computation steps left in the flow, else the performance gains from multi-threading in a RTL to Signoff flow could be significantly limited, according to Amdahl’s law.
With its unified client-server multi-cpu backplane, the Encounter platform has supported multi-processing since 1999, and has been continuously optimized for performance over time. Encounter’s focus is on overall flow performance from end-to-end, and we often achieve an average 2X- 4X runtime/memory footprint improvement per each major release. The latest release of the Encounter platform, called the Encounter Digital Implementation System is multi-cpu enabled by default.
In addition, to enable efficiency throughout the complete design flow, adjacent products such as sign-off analysis, DFM validation, the Virtuoso platform, functional verification and simulation are all multi-cpu enabled. It is Cadence’s goal to stay at the forefront in this, offering fully integrated and comprehensive parallel processing throughout back-end implementation.
No matter what new challenges may come down the road, the EDA industry must continue to help the semiconductor industry overcome obstacles and deliver new, innovative products despite the economic slow down.
To learn more about the state of the art in multi-process Encounter applications, join us at the Parallelism tutorial at the 46th Design Automation Conference – DAC this summer, featuring the Distinguished Engineer Tom Syprou of Cadence, together with Professor Kurt Keutzer of UC Berkeley, Tim Matsson and Michael Wrinn of Intel.