Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I was recently asked by an engineering manager if running IR drop analysis was really necessary. The argument to support his question was that his engineering team always over-designs the power rails, and so the risk of getting high IR drop was so small that analysis was not required.
The easiest way to answer his question was to relate what actually happened during the creation of a DAC demo a number of years ago.
The demo was designed to initially suffer from high IR drop in the center of the design, and the plan was to short the VDD of this region to a solid VDD, and hence fix the high IR drop. Figure 1 shows the initial IR drop analysis results, with the high IR drop in the center of the design. You can also see the solid VDD net just below the red region of IR drop.
While the added jumper did help reduce the highest IR drop in the center, it also enabled current to flow through a completely different path from the lower right boundary VDD I/O pad to the center of the design. This new path caused higher currents to flow around a memory, and resulted in new electromigration (EM) failures around the sense-amps of the memory. Figure 2 shows a zoomed in view of the lower right of the design, where you can see the added VDD jumper and the new EM failures.
When we saw this result, it surprised everyone involved and we were all experts with many years of experience in both chip design and IR drop analysis. No-one could have predicted how the addition of a small jumper in the center of the design could have caused new EM problems towards the corner of the design.
That's the reason why power rail analysis is required!
While we would like to believe that we can predict how current flows through the power network, in reality the current often flows unpredictably through multiple levels of interconnect and complex gridded power networks. It is the inability to predict how the current flows that forces the need for analysis. How can you possibly over-design the power rails when you don't know where, and how much, current is flowing though them?
Anyone have other thoughts on this?
Good article, giving a practical example. I am new to Voltagestorm or EPS and have used for static analysis only. However, it helped a lot in our design. I liked the feature in EPS, where it shows how much current flows through a node, the resistance, current density, etc. It also tells us in micro level what's the capacity of a metal strip to carry current. It helped us in defining the width of the metals to design analog power network.
I would also like to explore the dynamic EMIR flow.
Kari hits a great point on missing vias, or single vias where there was meant to be an array. Unfortunately neither DRC nor LVS can help you much, because of the gridded nature of the power networks. Tools like the Encounter Power System (and previously VoltageStorm), can easily find these problems and report them to you. It is even possible to find a VDD-VSS short, if you know what you're doing :)
I have empathy with Daniel, I had a similar experience when micro-probing an older design, except that my problem looked more like a volcano, the metal completely splattered ... the good old days, when we were lucky if DRC actually completed on designs!
In the olden days I watched my DRAM die under a microscope as a portion of the 6um metal interconnect would bubble and overheat due to excessive currents. IR drop and EM has always been an issue, even in the 6um era. I would've loved to use a software tool to pinpoint these failures so that I wouldn't need to make 21 spins of silicon to get my chip correct.
I completely agree, Pete. There are MANY reasons to do IR-drop analysis. One reason is that you can over-design the grid all you want, but if you happen to be missing a few key vias, that robust grid is not going to do what you think. IR-drop analysis can point out some things you didn't know were missing.
Also, it is important to not forget about the package. Designers really need to look at the die and the package together when doing IR Drop analysis.