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The nice thing about the EDP symposium (often referred to as the "secret DAC") is that
it favors open discussions around presented papers. It is a sound mix of
academic and industrial research and experiences and the goal is to foresee
what the coming design problems might be and propose either solutions or
alternatives. This year, the programme included a
number of interesting topics including parallelism/cloud-computing for EDA,
high level design/ESL, and 3D ICs.
I had the
privilege to present on 3D IC design - particularly the latest work/trends
around Through-Silicon Vias (TSV). For those of you that are new to this area,
here's an interesting article that helps understand the foundational elements: /blogs/di/archive/2010/03/29/My-DATE-With-3DIC-Technology.aspx.
The beauty and promise of this new technology is that it can inject a fresh
breath of air into the semiconductor industry and give life to a whole new world
of consumer end-applications. It can provide a huge paradigm shift to what can
be achieved in design performance, power, and form factor.
inconvenient truth is that the semiconductor industry is at crossroads. The
cost of doing design in the traditional 2D methodology is getting exhorbitant.
For instance, designing at 32/28nm incurs 3-4X the cost of design at 45nm
(spanning fabrication costs, design costs, process and mask costs). Additional
manufacturing effects like lithography, chemical-mechanical polishing, stress,
and double-patterning are rendering the move to advanced process nodes
exceedingly difficult. To make matters worse, we get hit with a double-whammy
since the time-to-production on advanced process nodes has increased
significantly, and that takes its toll on the profit margins for the industry.
is where the new 3D/TSV solution shows promise to be the panacea to the industry's
ailments. The biggest benefit it offers is the flexibility of heterogeneous
integration. Designers no longer need to move the entire System-on-Chip (SoC)
to the latest process node, thus eliminating a lot of the risks, costs and
time-to-market delays. Design companies can choose to keep their analog,
full-custom and memory IP at the older, safer process nodes while they move the
aggressive CPU/GPU/digital logic to advanced process nodes. Essentially,
designers now get the best-of-both-worlds by mitigating the cost, complexity,
risk, and development time. And the end-result is smaller and faster and
Williams from Future Tech and Sungkyu Lim from Georgia Tech also talked about
3D/TSV in their presentations. An interesting way of looking at the cost
savings from 3D/TSV is the following: Let's take a traditional methodology for
an SOC chip on a signle die with dimensions (L x L). The footprint/area of this
device would be L2 and the corner-to-corner distance would be 2L.
Now consider this chip to be implemented in 3D as a stack of 4 dies with each
die dimensions of (L/4 x L/4). The footprint/area of this device would be L2/4
(one fourth of the original). The corner-to-corner distance would be much
smaller to the original as well (L + h, where h is the height of the
stack). And this reduced area and corner-to-corner wire-length is what
effectively translates to significant benefits in performance and power for the
In the real
world, I see several semiconductor companies are now taping out real production
chips. Some of them are also using "Silicon Interposers" which are silicon
platforms with TSVs and enable different dies to be connected. It looks like
the light at the end of the tunnel is real, and not just a false hope. While
this technology and approach might not be for everybody (as was righly debated
at the EDP symposium), it is certainly is a differentiating strategy for the
select few semiconductor vendors who have embarked on this 3D/TSV path.
looked at this 3D/TSV technology? What's your take on it?
Thanks for your feedback. Samta seems to have addressed most of your questions.
As for 3D structures like FinFEt's, we are seeing foundries and IDM's pushing out the roadmap to 20nm and even to 15nm. There are still some challenges that need to be resolved before semiconductor companies can start using them.
You can think of TSV as further extension to CSP(Chip Stack package) technology that relied on wire bonds and silicon insulator to make connections hence leaving performance and power on the table. With the increased need of performance and power along with higher density/Form Factor, the TSV is the next step forward to the CSP technology.
I don't think that with TSV the older packaging trends will go away.They all will coexist and customers are going to make the cost and performance tradeoff depending the applications they are building for and the volumes they can make to make profits with any of these advanced methods.
Now to your question on Is TSV ready for Primetime? Not just yet in my opinion.. If you refer to the blog I wrote on the 3D subject(www.cadence.com/.../My-DATE-With-3DIC-Technology.aspx), you will see that there are some lingering questions out there that 3D community need to find answers for before it becomes mainstream. Having said that, within the past year itself the confidance on this technology has risen. Our Customers have done several test chips to show them the promise of TSV. Once ecosystem is ready (Which I think will be around 2013-2014), we should be in good shape.
Very well written Rahul.
Stacked die/Stacked CSP technology has been around for a while and seems to provide similar benefits of integrating die from various process nodes (although I think they need to be connected within the package substrate). Why use TSV? seems exotic. Is it ready for prime-time?
Talking of 3D structures, are 3D transistors being used in 32/28nm or not yet?
Harry, thanks for your feedback. Believe me, you should have stayed back for the second day - the discussion in the 3D session was very lively and multiple aspects of the TSV technology were highlighted - challenges, methodology, ecosystem and standards. Let's have a phone conversation and we can certainly bring you up to speed. Another valuable resource where you can find the latest relevant information is:
Though creating 3D stacks of silicon die and MCM's have been around for 20 years, it has progressed through various, improving methodologies - from wirebond, flip chip, Package-on-Package (PoP) to the latest through silicon vias (TSVs).
Of course, none of the benefits of TSV (smaller footprint, power, perfrormance) come for free. As you point out, we need new layout rules (for example alignments between die) and we have a new layout layer on the backside of the die to contend with. Also, the layout engine has to handle new layout and electrical features. Then we'll need a host of floorplanning capabilities (in 3D) and blockage rules (for the TSVs). And, there are a slew of thermal and mechanical issuess (how are we going to get rid of the thermal hot-pockets; how do we deal with mechanical stress), and... the list goes on.
And, this is where Cadence has worked extensively with the ecosystem to provide the necessary tools to handle these challenges. From 3D auto-interactive floorplanning and power-planning; 3D-aware implementation engines for placement, optimization, and routing; 3D-aware extraction and analysis (thermal, power, signal integrity...); to chip-package-board co-design capabilities.
Let's connect and have a more in-depth conversation.
I was at EDPS last week and caught some of the presentations you mention, but unfortunately could not attend the 2nd day when you presented. I'm hoping to get the slides once they are posted to the EDPS website.
I'm not an expert at 3D packaging by any means (nor at packaging in general), but I was around some number of years ago when MCMs (multi-chip modules) were going to deliver very similar benefits to the ones that 3D packaging techniques are aiming to provide. I was one of those who put his subsystem design into an MCM, but never got to see it completed because the MCM vendor went out of business, and not much later the entire MCM industry went away.
The challenge to the MCM industry was that it provided the ability to achieve a level of integration in a size footprint with lower power but technology would catch up within a year to where the same device could be delivered in a single IC. This one year lead was the benefit, but the downside was a large complexity and yield issues along with the need to identify and test known good die, manage thermal issues,etc.
Certainly our packaging technologies have improved since the MCM days. Still, the mechanical challenges for 3D must be pretty daunting. Hopefully the process is mature enough to produce high yield and the time-to-market advantage is more than a year. I'll be watching closely.