Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
With DAC 2010 rapidly approaching, we can again expect that lots of EDA and
IP vendors will use “mixed signal” somewhere in their company’s messaging. Last
year it seemed that nearly everyone wanted to jump on the mixed signal
“bandwagon” … so what caused this sudden jump in interest in mixed signal?
We all know that mixed signal design is not new. It’s been around for about
20 years (give or take), but there has been a shift in the types of mixed
signal designs that are being developed.
In the past, a mixed signal design was typically a pretty small design that
was created using a manually-driven design methodology. Design engineers drew schematics
and simulated the design, while layout designers created the physical layout
based on the schematics and constraints from the design engineers. Custom
schematic editing and layout tools such as Virtuoso were used for these
As the digital content of these mixed signal designs grew beyond a manageable
number of instances, a purely manual implementation approach rapidly became a
major bottleneck. Instead, design teams looked to more automated digital
implementation solutions, based on standard ASIC methodology. Here at Cadence,
we created a specific product for such designs, called Virtuoso Digital
Implementation (known as VDI), which complements Virtuoso and enables automatic
digital implementation for up to 50K instances. VDI has seen rapid growth,
which reflects the growth in these types of mixed signal designs.
In the past couple of years, there have been a growing number of mixed signal
System on Chip (SoC) designs … very large, very complex designs that contain multiple
digital and analog components fully distributed throughout the chip. A simple example of such a design is shown
in Figure 1.
Figure 1: Example mixed signal SoC design
There are many additional design and methodology challenges associated with developing
this type of advanced mixed signal SoC chip, mostly related to size and functional
complexity. It all starts with early functional verification, where simulators
are challenged to simulate huge netlists over large timescales in order to
comprehensively validate that the design meets the functional specification.
The challenges continue through physical floorplanning, analog/digital/mixed
signal implementation and eventually design signoff prior to tapeout.
Large designs mean that power management is critical, while fully
distributed analog and digital components force attention to noise management.
The advanced process technology, required to enable such large amounts of
functionality to be integrated onto the same die, forces even more attention on
design for manufacturing techniques, else low yields can be expected.
These design challenges, plus industry predictions that practically every
design will be a mixed signal design in the not-too-distant future, are gaining
attention for obvious reasons.
Cadence has already focused on all components within our mixed signal design
flows to ensure that such complex SoC designs can be efficiently designed. If
you are going to DAC, stop by our booth (#1334 in Hall B) and learn why the EDA
industry is positioning Cadence as a true leader in mixed signal.