Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings to achieve routing success?
Fortunately, the application note on NanoRoute Recommended Options is available to help answer these questions. Many of you are utilizing it already but I wanted to highlight it here because it has been recently updated. If you have not referenced this app note in the past, I highly recommend using it. The app note provides the recommended NanoRoute settings with a focus on 32nm and 28nm design nodes. But it is useful regardless of what process node you're designing at. It covers:
I personally reference multi-cut via insertion flows on pages 5 and 6 on a regular basis. These flows describe a good, better and best approach providing the options to run concurrent and/or post-route insertion of multi-cut vias.
But multi-cut via insertion only works if you have a proper set of multi-cut vias defined. If you're using one of the major foundries they often will provide a technology LEF file with an optimal set of vias for NanoRoute.
If you are developing your own technology LEF consider using the generateVias flow. This flow is described in Solution 11774588. The generateVias command, introduced in EDI 11, will analyze the VIARULE ... GENERATE DEFAULT rules and the cut layer rules (spacing, width, enclosure, etc.) in the LEF to create the optimal set of vias for NanoRoute. generateVias usage is supported for 40nm and below.
For example, you describe a template for how the vias should be generated:
VIARULE M7_M6 GENERATE DEFAULT LAYER Metal6 ; ENCLOSURE 0.005 0.03 ; LAYER Via6 ; RECT -0.035 -0.035 0.035 0.035 ; SPACING 0.14 BY 0.14 ; RESISTANCE 5.000000 ; LAYER Metal7 ; ENCLOSURE 0.005 0.03 ;END M7_M6
Then prior to NanoRoute run generateVias to optimal vias:
I hope this helps you achieve routing success!
- Brian Wallace
Yes, in EDI System 10.1 generateVias will generate vias based on the VIARULE ... GENERATE DEFAULT statement. EDI 11 utilizes the same VIARULE statements as well as the VIA technology rules defined for the via layers to generate the vias. EDI 10.1 will not look at the via layer rules, only the VIARULE.
Is this feature included in EDI 10 also?