Digital Design

Beyond Moore's Law: Advances in Modern Semiconductor Design

2026-08-01T00:45:00Z

The Shifting Landscape

For decades, Moore's Law delivered a simple promise: more transistors, more performance, and lower cost. Today, that equation is changing. As transistor scaling approaches physical and economic limits, innovation is shifting beyond the transistor itself—into advanced packaging, heterogeneous integration, chiplets, memory architectures, and system-level optimization.

This blog explores the major shifts shaping this transformation—from transistor architecture evolution and manufacturing complexity to chiplet-based design, UCIe standardization, and high-bandwidth memory.

Moore's Law and Its Limits

The Original Promise

Gordon Moore's 1965 observation originally described a doubling roughly every year; he later revised it in 1975 to roughly every two years. This exponential trajectory held remarkably true for decades:

Intel 4004 (1971): 2,300 transistors
Pentium (1993): 3.1 million transistors
Apple M1 Ultra: 114 billion transistors
NVIDIA Hopper: 80+ billion transistors

The Slowdown Factors

However, pure transistor scaling is no longer the whole story. Several forces are slowing traditional Moore's Law:

Physics limits: short-channel effects, leakage, and quantum-mechanical effects become more severe at advanced nodes.
Lithography complexity: increasing EUV process complexity and cost at advanced nodes
Economic pressure: leading-edge design and productization costs can reach extremely high levels, with advanced-node programs potentially exceeding $1B overall.
Power density: Dennard scaling ended circa 2006.

As a result, traditional scaling is no longer sufficient on its own.

Inverse Moore's Law and Yield Economics

Even as transistor scaling slows, the cost of delivering useful computing capability at the system level often continues to decline through architectural innovation, software optimization, and economies of scale, where the cost of delivering a given amount of functionality tends to fall over time. For example, systems that once cost millions are now consumer-grade products.

But at advanced nodes, yield economics become a major constraint:

Larger dies will have more defects leading to lower yield
Advanced nodes (3nm and below) result in exponentially higher cost per die.

This creates a critical challenge: Building larger monolithic chips is becoming economically unsustainable. This pressure drives the industry toward alternative design approaches.

Transistor Architecture Evolution

Planar MOSFET: Dominant through roughly the 28nm era

The workhorse of early semiconductor scaling. The gate sits on top of a flat channel, controlling current flow from above only. Simple and cost-effective at larger nodes, but as dimensions shrank below 28 nm, the gate lost adequate control over the channel, leading to unacceptable leakage currents.

FinFET: Mainstream at advanced nodes through the 2010s and into the 2020s

Intel introduced FinFETs at 22nm. The channel rises as a vertical "fin" with the gate wrapping around three sides, dramatically improving electrostatic control. This enabled scaling down to 5 nm with manageable leakage and better performance-per-watt. Fin height variability and patterning at tighter pitches are its key manufacturing challenges.

GAAFET: Emerging in leading-edge production and expected to expand further

Gate-All-Around FETs (nanosheets/nanowires) represent the frontier. The gate completely surrounds the channel, providing the strongest electrostatic control and the sharpest ON/OFF switching. Manufacturing requires selective layer deposition, channel release etching, and precise nanosheet thickness control—significantly more complex than FinFET fabrication.

These innovations extend Moore's Law, but at the cost of massive manufacturing complexity.

Manufacturing: FEOL, MOL, BEOL

Modern chip fabrication is divided into three precisely orchestrated stages, each building on the previous one.

The Fabless Revolution and Rising Design Costs

The semiconductor industry has undergone a fundamental structural transformation. As manufacturing complexity increases, so does cost. Where companies once designed and manufactured their own chips (IDM model), the prohibitive cost of modern fabs—often exceeding $10-20 billion has left only a small number of companies capable of operating leading-edge manufacturing facilities.

Today, leading-edge logic manufacturing is concentrated among Intel, TSMC, and Samsung.

This has fundamentally reshaped the industry.

Most other major semiconductor companies—Qualcomm, Broadcom, NVIDIA, and AMD—have transitioned to a fabless model, focusing on design while outsourcing manufacturing.

Meanwhile, IC design costs have skyrocketed. A typical chip costs $10-100M to design; a state-of-the-art microprocessor can exceed $1B. Verification can account for a significant majority of development effort in advanced SoC programs. Product revenues must be roughly 10X development costs to justify investment, creating intense pressure on first-time-right silicon.

These economic pressures demand new design methodologies.

Chiplets and Heterogeneous Integration

Instead of building a single 800 mm² die that may suffer from poor yield, manufacturers can construct a system from multiple smaller chiplets with higher individual yield and lower overall cost.

To address yield and cost challenges, the industry is moving toward building systems from multiple cooperating dies or chiplet-based architectures instead of one monolithic chip.

Chiplets

2.5D vs 3D Integration

Smaller functional dies that together form a complete system. Each chiplet implements a specific function—compute (CPU/GPU/AI), memory, IO/SerDes, or accelerators.

Key advantages:

Higher individual yield per die
Reuse across product lines
Mix-and-match process nodes (3nm + 7nm + 28nm)
Only known-good dies assembled

2.5D: Side-by-side dies on an interposer with fine-pitch routing. Better heat spreading, predictable power delivery. Ideal for logic + HBM configurations.

3D: Vertical die stacking connected via Through-Silicon Vias (TSVs) or hybrid bonding. Extremely high bandwidth and density, but poses thermal challenges as upper dies trap heat. Maximum density for memory stacks.

Chiplets mark a shift toward system-level design instead of single-chip scaling.

UCIe: The Universal Die-to-Die Standard

As chiplet adoption grows, a new challenge emerges: How do chiplets from different vendors communicate? Without standardization, proprietary interfaces limit ecosystem growth.

UCIe has the potential to do for chiplets what PCI Express did for expansion cards -create an open ecosystem where components from different vendors can interoperate through a common interface.

Universal Chiplet Interconnect Express (UCIe) is the industry's answer—an open standard that defines high-bandwidth, low-latency, power-efficient die-to-die communication inside a single package.

Interoperability	Reuse and Scale	Performance	Simplified EDA
Build systems from a multi-vendor chiplet ecosystem	Faster time-to-market, lower design risk	High-performance multi-die systems at package scale	Standardized signoff for die-to-die interfaces

UCIe transforms chiplets into a true modular ecosystem.

These system-level innovations introduce new verification, implementation, and signoff challenges. Engineers must now validate multi-die connectivity, advanced package interactions, thermal behavior, power integrity, and chiplet interoperability. As a result, EDA flows are expanding beyond traditional SoC implementation into system-level design and analysis.

High Bandwidth Memory: The AI Workhorse

Many AI and HPC workloads are fundamentally memory-bandwidth limited, rather than purely compute-limited.

In modern AI accelerators, compute resources often sit idle while waiting for data. HBM addresses this bottleneck by dramatically increasing memory bandwidth, allowing GPUs and AI processors to remain fully utilized.

How HBM solves this:

Multiple DRAM dies stacked vertically
Through-silicon vias (TSVs) for vertical connections
Silicon interposer for dense die-to-processor wiring
Short, fast data paths to the GPU/AI accelerator

HBM provides:

High bandwidth and energy-efficient data movement
Latency benefits depend on system architecture and access pattern

HBM in modern systems:

Requires advanced 2.5D/3D packaging
Tightly coupling memory with GPUs/AI accelerators within a single package
Short data paths for faster access

The Road Ahead

The future of semiconductor innovation will not be defined by transistor scaling alone. Success increasingly depends on how effectively designers integrate advanced process technologies, packaging, memory, interconnects, and software into complete systems.

Moore's Law was never just about shrinking transistors—it was about continuous progress in performance, cost, and capability.

That progress continues, but through a different paradigm:

GAAFETs pushing transistor scaling further
Chiplets overcoming yield and cost barriers
UCIe enabling ecosystem-level integration
HBM delivering the bandwidth that AI demands

In the Beyond-Moore era, the package is becoming the new system, and system-level optimization is becoming the new scaling strategy.

To learn more about advanced semiconductor topics, enroll in our Semiconductor 101 v3.0 training and earn a Cadence Digital Badge.

To learn about other courses, see the Learning Map and take training courses in different areas of chip design based on your interests.

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Power Grid Verification Flow: A Methodology for High-Coverage Signoff

2026-07-31T16:30:00Z

As semiconductor designs continue to scale in complexity, ensuring robust power integrity becomes one of the most important challenges in design signoff. Power grid weaknesses can appear as IR drop violations, excessive supply noise, timing degradati...(read more)

The PPA Grand Prix: Fine-Tuning Designs with Advanced Synthesis

2026-07-30T12:30:00Z

Ever watched a Formula One race and wondered what makes the winning car just a little faster than the rest?

It's rarely one big breakthrough.

It's hundreds of tiny optimizations working together—better aerodynamics, smarter tire strategy, precise tuning, and countless engineering decisions made behind the scenes. The difference between first place and the pack is often measured in milliseconds.

Advanced synthesis is no different.

Achieving the best power, performance, and area (PPA) requires far more than pressing "Run." It requires understanding how to fine-tune constraints, guide optimization strategies, leverage physical awareness, analyze timing bottlenecks, and make informed trade-offs throughout the flow.

Every picosecond recovered, every microwatt saved, and every area improvement gained is another advantage in the race toward design closure.

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That's where the Advanced Synthesis with Genus Stylus Common UI training comes in.

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Designed for engineers ready to move beyond the fundamentals, this course helps you transition from simply running synthesis to understanding and influencing the optimization decisions that drive superior QoR.

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We provide dynamic video content for each training lab to support your learning journey. Every lab module includes a demo-style walkthrough of the instructions, making it easier to ramp up the tools and troubleshoot any steps. Whether you're just a beginner in synthesis or already have some experience, we're here to help you navigate it confidently.

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As a next step, you can further leverage the vast database of videos and detailed training on Cadence Application Support and Knowledge Portal (Cadence login required).

Bonus Features

Enhance the Genus Synthesis Solution experience with short videos: Genus Synthesis Solution: Video Library.
Get ready for the most thrilling experience with Accelerated Learning!
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Bite-Sized Learning for Big SoC Challenges: Genus Training Bytes - Digital Design - Cadence Blogs - Cadence Community

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Your Phone Gets Updates, So Does Your Synthesis Expertise!

2026-07-28T04:54:00Z

Most of us update our phones without ever knowing about the coolest new features hidden inside. The same can happen with synthesis tools—powerful capabilities get added, but they often remain undiscovered.

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🔹 Improvements in Handling Constant Flops – Explore enhancements that help identify and optimize more constant sequential logic.

🔹 What Is Cut-Based Mapping? – Discover an advanced logic-mapping technique that improves technology mapping efficiency and quality of results.

🔹 Commands and Attributes to Control Partition-Based Synthesis Multiple Instantiated Modules (PBS MiM) Flow – Understand the controls available for optimizing synthesis of highly repetitive designs.

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Start Learning Today

Don't let great features stay hidden. Explore the latest Genus Training Bytes and unlock what's already waiting in your toolbox.

Watch the latest Training Bytes and accelerate your understanding of the newest Genus capabilities:

Clock Gating History Recording (Video)

What Is Common Front End (CFE)? (Video)

Improvements in Handling Constant Flops (Video)

What Is Cut-Based Matching? (Video)

Commands And Attributes To Control PBS MiM Flow (Video)

What Is Advanced Structuring? (Video)

What Else Can You Explore at the ASK Portal?

Free Online Trainings: The Online Trainings are free for all Cadence customers with a Cadence ASK Account. For instructor-led training sessions, "Live" or "Blended," please contact Cadence Training.

Further enhance the Genus Synthesis Solution learning experience with short videos: Genus Synthesis Solution: Video Library.
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The Cadence YouTube channel hosts a Customer Education Training Bytes channel.

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Bite-Sized Learning for Big SoC Challenges: Genus Training Bytes - Digital Design - Cadence Blogs - Cadence Community

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Modular Magic: Accelerate Chip Design with Genus Bottom-Up Flows - Digital Design - Cadence Blogs - Cadence Community

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Still Using Synthesis Tricks from Your "Golden Script" Folder? Consider Upgrade!

2026-07-23T05:39:00Z

Ever looked at an old synthesis script and thought, “Who wrote this masterpiece of confusion?” Then realized… It was you. Six months ago. You're not alone.

Every engineer has one. That mysterious folder containing TCL scripts copied from project to project, generation after generation. Nobody remembers who created them. Nobody wants to modify them. And somehow they're still running.

When a new project begins, the ritual is familiar:

"Copy the scripts."

"Update a few paths."

"Hope for the best."

While legendary scripts deserve respect, modern SoC designs have evolved significantly. Timing targets are tighter, power goals are more aggressive, and design complexity continues to grow. Successfully achieving the best Power, Performance, and Area (PPA) requires more than relying on yesterday's synthesis habits—it requires understanding today's synthesis capabilities and methodologies. The Genus Synthesis Solution is designed to help deliver optimal productivity and PPA during RTL synthesis.

Because sometimes the best optimization isn't another synthesis run. It's upgrading the synthesis knowledge! That's where the Genus Synthesis Solution with Stylus Common UI training comes in.

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Whether you're new to synthesis or a seasoned designer looking to refresh your expertise, this course helps you move beyond inherited scripts and develop a deeper understanding of the Genus synthesis flow, modern optimization techniques, and debugging strategies needed for today's complex designs. The training covers design constraints, timing analysis, physical synthesis, low-power optimization, DFT constraints, and complete synthesis flow execution to optimize area, timing, and power.

Not Just Slides — Hands-On Labs Included

Let's be honest. Nobody becomes a synthesis expert by reading PowerPoint slides alone. That's why the training includes hands-on labs that cover realistic design scenarios, complete with guided instructions and exercises. And if you get stuck?

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How to Run the Setup for Synthesis, Load Libraries, and Design And Elaborate The Design Module in Genus Synthesis Solution? (Video)

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Complete the training and earn your Cadence Digital Badge. It's a great way to showcase your expertise and demonstrate your commitment to staying current with modern synthesis methodologies. And unlike timing violations, this is something you'll actually want to show people.

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After completing this training, you may experience a sudden urge to clean up old synthesis scripts, remove obsolete commands, and finally understand what that mysterious TCL procedure actually does. Results may vary. 😄

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Short Training Bytes/Videos:

Enhance the Genus Synthesis Solution experience with short videos: Genus Synthesis Solution: Video Library

Did You Know?

The Cadence YouTube channel hosts a Customer Education Training Bytes channel.

The latest trendy channel is Customer Education – Shorts - YouTube, where you can view a variety of training bytes for which you do not need a Cadence ASK account.

Bite-Sized Learning for Big SoC Challenges: Genus Training Bytes - Digital Design - Cadence Blogs - Cadence Community

Your Skills Deserve a Passport: Showcase Your Expertise with Digital Badges - Digital Design - Cadence Blogs - Cadence Community

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From Chaos to Clarity: Mastering PBS MiM Flow Without the Land Disputes - Digital Design - Cadence Blogs - Cadence Community

Might of Design Exploration: Deep Dive of Exploration Techniques in Stratus HLS

2026-07-22T09:49:00Z

Stratus HLS's behavioral design methodology enables easy exploration of multiple algorithms and architectures to achieve better trade-offs among area, power, and latency requirements.

In this blog, we'll delve into the various exploration techniques that Stratus HLS provides and how they can revolutionize your design process.

Understanding Exploration Techniques

Exploration techniques in Stratus HLS primarily focus on evaluating microarchitecture decisions as the design evolves, considering trade-offs to produce different solutions. Stratus HLS determines the behavior of a synthesized design from the SystemC source, but there are many ways to transform the same SystemC into RTL.

Microarchitecture control is how you influence that transformation without changing the source code.

The microarchitecture is controlled by three mechanisms, which can be used independently or together:

Synthesis control attributes
Synthesis directives and Tcl commands
Active module parameters
A fourth dimension is configurable I/O interfaces that are managed separately through io_config and the generated Interface library, and controls what the module's ports look like at each abstraction level. A configurable system model enables trade-offs between protocols and data types without modifying the core design.

Let us further explore how to apply these mechanisms.

Synthesis Control Attributes

Synthesis control attributes affect synthesis decisions globally or individually for each hls_config. As tabulated here, there are three different ways to set the synthesis attributes:

Scope	Method of Setting	Example
Project-wide (All configs)	set_attr <outside any config block>	set_attr clock_period 7.5
Per hls_config	--attr = value on define_hls_config	--sched_asap=on
Batch across multiple configs	set_attr with find	set_attr cycle_slack 1.2 [find -hls_config <configName>]

Any typical exploration pattern defines a family of configs, then differentiates them. The most frequently used configs are, hls_config, sim_config, analysis_config, cov_config, equiv_config, io_config, logic_synthesis_config, power_config, sim_config, system_config.

These basic setup parameters help in exploring how timing, pipelining, and memory organization interact to shape the final RTL architecture.

Setting the stage for the HLS: The synthesis setup begins by defining a clock period and a default input delay, thereby establishing the effective timing budget available for internal scheduling and datapath generation.
- set_attr clock_period 5
- set_attr default_input_delay 1.5

Defining multiple HLS configurations for exploration: This is a classic design-space exploration setup: same functionality, different synthesis strategies. To explore multiple implementation styles of the same design, in this example, four HLS configurations — BASIC1, FLATTEN, UNROLL, and DPOPT are created.
- define_hls_config dut BASIC
- define_hls_config dut FLATTEN -- flatten_arrays=all
- define_hls_config dut UNROLL -- unroll_loops=on
- define_hls_config dut DPOPT -- dpopt_auto=all

Other attributes: Multiple such attributes are available in a structured manner to tune the design for better and a balanced tradeoff between area, performance, and timing closure
- set_attr flatten_arrays all [find -hls_config FLATTEN*]
- set_attr cycle_slack 2 [find -hls_config *]

The clock period is a primary timing knob used to define the target cycle time for scheduling and datapath synthesis. To go beyond the basic clock setting, Stratus provides additional tuning knobs. These parameters determine how aggressively your logic can be packed, and this flexibility enables you to make your design more or less aggressive in packing logic into clock cycles, ultimately impacting latency, timing closure, and a balanced QoR.

cycle_slack: Specifies an amount of time in each clock period that is to be reserved for use by downstream tools.
path_delay_limit: Specifies a variable upper bound of the allowable length of timing paths, true or false, in your design

Here is the differentiation of a design with the application of slack or no slack:

No Slack	With Slack
Faster Parts	Smaller Parts
More Registers	Fewer Registers
Higher Area	Better QoR balance

When timing cannot be met, StratusHLS reports scheduling failures, Loop Carried Dependency [LCD] violations, and resource conflicts. By setting latency constraints, you can explore the impact of different latency values on your design's performance and area. It is important to note that the latency constraints are a major cause of scheduling failure.

Common causes include data dependencies, insufficient operator timing, conflicting protocol boundaries, resource conflicts, and incompatible loop-carried dependencies. When this occurs, Stratus HLS reports minimum achievable latency, and error diagnostics identify blocking constraints. Latency constraints in Stratus HLS specify the maximum number of cycles a region is allowed to consume, guiding the scheduler’s trade-offs among parallelism, resource usage, and performance.

In summary,

Tighter latency ⇒ More parallel hardware, less sharing.
Looser latency ⇒ Serialized execution, reduced area.

Synthesis Directives and Tcl Commands

Directives and Tcl commands target specific objects in the source: loops, arrays, regions, and ports. They are the mechanism for fine-grained microarchitecture control. In HLS, elaboration is the stage where the design hierarchy, loops, variables, interfaces, and internal structures are fully understood by the tool.

When to use:

Use synthesis directives when you are working with the source code. Let us see an illustration of the usage as a source directive in the code.
while (1){

HLS_PIPELINE_LOOP (HARD_STALL, 1, "MAIN_LOOP");

vin = din.get();

vout = f( vin );

dout.put( vout ); }
Use Tcl commands, when keeping synthesis policy separate from behavioral specification, or when you need to vary the policy per hls_config.

In the project file:

define_post_elab_tcl {

pipeline_loops -type HARD_STALL -initiation_interval 1 [find -loop MAIN_LOOP] }

In the source code:

MAIN_LOOP: while (1){

vin=din.get(); vout=f(vin); dout.put(vout);}

Several synthesis directives and their equivalent TCL commands are available. You can refer to the HLS reference guide for further information on these.

Directive Name	Effects
HLS_UNROLL_LOOP	Unrolls iterations; Increases parallelism; Trades area for latency
HLS_PIPELINE_LOOP	Pipelines the loop; Overlaps iterations; Trades area for throughput
HLS_CONSTRAIN_LATENCY	Constrains cycle count; Forces parallelism or serialization
HLS_FLATTEN_ARRAY	Forces array to individual scalar registers, enabling parallel access.
HLS_MAP_TO_REG	Maps an array to registers
HLS_MAP_TO_MEMORY	Maps an array to a named memory instance
HLS_BREAK_PROTOCOL	Insert a cycle boundary at a specific protocol point.
HLS_DPOPT_REGION	Applies data path optimization to the enclosed arithmetic

The table lists several key directives and their microarchitectural effects.

Configurable I/O Interfaces

In High-Level Synthesis, your algorithm stays the same, but the way it talks to the outside world is completely configurable. Configurable I/O interfaces are managed separately from the microarchitecture controls above.

If you need,

Low latency? Use direct IO.
Safe communication? Add a handshake.
Processing large data? Go memory or streaming.

This means the same design can plug into completely different systems just by changing the interface configuration. You can control the abstraction level and protocol of the module's ports without changing the DUT or testbench code.

Stratus HLS introduces the following interface types to optimize your design.

An ‘io_config’ to control which ports and channels are used to connect modules in the system.
There are predefined i/o configs:
- PIN Level: Pin-accurate protocol; synthesizable; cycle-accurate
- TLM: Transaction-level modeling; loosely timed; faster simulation
An interface generator (bdw_ifgen) that produces C++ interface classes from interface definitions (.bdl files).

How to Use Compile-Time Configuration and Abstraction to Make a SystemC Design Adaptable Across Multiple Data Types

In SystemC-based HLS flows, developers often work with multiple numeric types such as sc_int, sc_bigint, and ac_int. Each has different precision capabilities, performance implications, and synthesis characteristics. Without abstraction, switching between these types means rewriting large portions of code.

Data types in the source code - defines.h;

Data types in the source code - file.h;

Data types in the source code - file.cpp

The image depicts the way of configuring the design interfaces for the above-defined data types

Exploring Using Pipelining Constraints

Pipelining constraints are one of the primary exploration axes in Stratus HLS because they directly trade off throughput vs. area, latency, resource sharing, and clock frequency feasibility. Through pipelining, Stratus HLS allows designers to generate multiple microarchitectures from the same source code, where a single untimed algorithm can yield multiple microarchitectures, each with vastly different performance and cost, simply by tuning pipelining.

What Do the Pipelining Constraints Help Resolve?

When pipeline constraints are applied, Stratus HLS may report that a requested initiation interval is not achievable, that Loop-carried dependencies prevent pipelining, or that resource or memory conflicts stall the pipeline.

These reports help identify and, in turn, resolve:

Algorithmic bottlenecks
Refine pipeline constraints
Adjust loop structure or memory layout

Applying pipelining constraints transforms sequential algorithms into high-performance hardware pipelines while allowing designers to navigate a wide design space using Initiation Interval, Stall modes, as prime parameters.

The image indicates the area numbers for different configurations.

Active Module Parameters

Active module parameters are a configuration-level abstraction. It does not require any Tcl scripts or source directives. Internally, these parameters translate into synthesis directives at post-elaboration. For training and design-space exploration, Active Module Parameters are particularly valuable because they let you create configuration variants, all without touching the source code.

Active module parameters are specified in define_hls_config using forms such as:

-parameter = value
-parameter:object = value

These parameters execute Tcl bodies that generate the underlying Stratus directives automatically. Example usage of the parameters is as shown:

define_hls_config mymod CFG1 -main_latency=10
define_hls_config mymod CFG2 -pipeline_loop:my_loop=1

Here is the table listing the parameters that allow you to steer the micro‑architecture without rewriting the source code — shifting your role from coder → architect.

Design Intent	Parameter	Controls
Latency Control	-main_latency, -constrain_latency: <loop>	Controls total execution cycles of function/loop
Loop Pipelining	-main_pipeline, -pipeline_loop:<loop>	Enables overlapping execution of loop iterations
Data Path Optimization	-dpopt_region:<region>, -dpopt_function:<fn>	Optimizes operator sharing, restructuring, and logic mapping
Memory vs Register Mapping	-map_array:<array>	Chooses how arrays map to hardware: RAM / Registers / Flattened

Stratus HLS Integrates with Cerebrus for Automated Exploration

Cadence Cerebrus is a design optimization tool that applies machine learning (ML) to achieve optimal PPA. When applied to Stratus HLS, the goal is to produce the optimal RTL from a behavioral model rather than to optimize a fixed RTL. The Stratus-Cerebrus integration automates exploration and guides it with ML to converge on an optimal result.

Cerebrus is configured with a set of primitives that define the space to be explored and a cost function that determines how PPA will be evaluated. Based on the metrics and primitives set for those scenarios, Cerebrus learns which primitives move the results closer to an optimal target. Cerebrus further explores the values of the enabled primitives and seeks the set that yields the best PPA. Stratus HLS provides utilities for specifying project primitives.

The image illustrates the power of using Cerebrus to explore a design.

How Is HLS Design Space Exploration Performed with Cerebrus Primitives?

HLS is not just about writing SystemC code, but about exploring architectural choices intelligently. And Cerebrus is used in Stratus HLS to accelerate the production of the optimal RTL, rather than to optimize a particular RTL. The flow begins with an hls_config that successfully produces RTL, but that does not yet yield optimal PPA. Here are the key advantages of using Cerebrus for exploration:

No code changes required
- All design exploration is controlled externally via Cerebrus scripts
- The original SystemC/HLS design remains untouched
Exploration-driven optimization
- Each setup defines a search space of architectural and synthesis choices
- Includes constraints and goals for PPA evaluation
Automated iterative flow
- Cerebrus repeatedly runs the Stratus HLS synthesis flow
- Automatically adjusts configurations between runs to explore better solutions
Scenario-based exploration
- Each combination of settings creates a unique design scenario
- These scenarios are stored as hls_configs in the Stratus database
Seamless integration with Stratus
- Generated scenarios behave like standard HLS configurations
- Can be further analyzed using the Stratus IDE
Real-time tracking and analysis
- Cerebrus UI provides visibility into:
  - Exploration progress
  - Scenario completion status
  - Comparative evaluation of results

This image illustrates the typical inputs known as primitives in Cerebrus. The details defined by the "max_scenarios" option in the init_cerebrus script help in exploring the design, including the other parameters.

This is design space exploration for multiple combinations of timing constraints, scheduling strategies, and resource optimizations automatically explored by Cerebrus. Instead of manual tuning, exploration is automated, and the design space is covered efficiently, leading to faster identification of optimal architecture.

This image depicts the five design exploration scenarios (scenario_1 → scenario_5) evaluated against a base configuration.

Cerebrus rapidly explores multiple HLS optimization strategies and automatically converges on configurations delivering ~25% better QoR without increasing runtime.

The images show the results indicating the best design, enabling optimal tradeoff decisions

Conclusion

Stratus HLS is a game-changer in the world of digital design. The exploration techniques provide unparalleled flexibility and control, allowing you to optimize your designs for area, performance, and power. Exploration is achieved by defining multiple hls_config and systematically varying synthesis attributes, directives, scheduling contexts, datapath partitions, interfaces, and parameters, manually or via Cerebrus, to analyze and compare QoR trade-offs.

Explore deeper insights into Stratus HLS and digital design methodologies:

Stratus HLS - Digital Design - Cadence Blogs - Cadence Community

Enhance your expertise through the following relevant training:

SystemC for High-Level Synthesis Training Course

Stratus-HLS Basic Training

Cadence Cerebrus Intelligent Chip Explorer

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Accelerate Design Signoff with the Updated Cadence Voltus Training Kit

2026-07-21T03:44:00Z

By Ronen Stilkol, Senior AE Architect As advanced-node and 3D-IC designs push higher performance into tighter power, thermal, and packaging constraints, engineers must understand how the die, package, board, activity profile, and implementation flow ...(read more)

Cadence RTL Design Studio: Built for the Full PPAC Journey

2026-07-14T17:00:00Z

If you've used Joules RTL Design Studio, you already know what it can do. Now it has a name that matches its full potential.

We're renaming Joules RTL Design Studio to Cadence RTL Design Studio. The product isn't changing, just the name.

Why Is the Name Changing?

When Joules RTL Design Studio launched, it expanded upon the Joules RTL Power Solution by adding visibility into performance, area, and congestion alongside power. But the "Joules" name stuck—and with it, the perception that this was primarily a power tool. It isn't. It never was just power.

Cadence RTL Design Studio is a full PPAC solution. It gives front-end designers early, accurate insight into power, performance, area, and congestion—all before handoff to implementation. The new name makes that clear from the get-go.

What It Does

Cadence RTL Design Studio delivers up to 5X faster RTL convergence and up to 25% improvement in quality of results (QoR) by bringing physical design feedback to the RTL stage—where changes are fastest and cheapest to make.

Key capabilities include:

Full PPAC visibility at RTL – Identify timing, congestion, power, and area issues early, before they become costly implementation problems.
Intelligent RTL debugging assistant – An expert system that triages violations, explores what-if scenarios, and provides actionable guidance to resolve issues directly in the source code.
Proven engine accuracy – PPAC estimates are driven by the same trusted engines as Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, so designers can trust that RTL-stage decisions will track with production implementation.
Unified cockpit – A single GUI for RTL analysis, schematic cross-probing, layout feedback, and design exploration.
AI-powered design exploration – Integration with Cadence Cerebrus^® Intelligent Chip Explorer enables generative AI-driven exploration of floorplan optimization, frequency vs. voltage tradeoffs, and more.
Prototyping support – Designers can explore and prototype design decisions prior to committing to place and route, reducing costly late-stage iterations.

The Bigger Picture

For too long, RTL designers operated separately from implementation engineers. Problems that could have been identified and resolved quickly during the RTL phase were instead found later, causing costly revisions and delaying product release.

Cadence RTL Design Studio closes that gap. It shifts left the visibility and intelligence implementation teams have always had, putting them directly in the hands of front-end designers at the moment they're most useful.

The name change goes beyond appearance; it indicates that this tool supports the entire PPAC process—from initial RTL design to final production implementation.

Learn more about Cadence RTL Design Studio.

The product formerly known as Joules RTL Design Studio is now Cadence RTL Design Studio. No changes are being made to the product at this time.

The Truth About Complete DFT Flow: What Most Engineers Miss

2026-07-14T05:30:00Z

Design for Testability is a critical step in achieving high-quality silicon. In this Training Bytes blog, we are going to explore implementing an efficient DFT flow using the Genus Synthesis Solution, covering key concepts such as synthesis with test, scan insertion, test readiness, and preparing your design for ATPG with Modus and for fault diagnostics.

Synthesis with DFT
In this section, we introduce the DFT implementation flow using the Genus Synthesis Solution. These videos focus on preparing your design for test by integrating DFT architectures early in the flow.

Ever wonder how DFT fits seamlessly into your synthesis flow? Check out our short byte on YouTube titled: A Design with Test Circuit where you can explore your design with test structures.
Adding test structures in your design requires some Basic DFT Rule Checks. The intent of these checks to ensure the elements put in the scan chains are shifting data properly.
DFT isn’t just an added step, it is the backbone of test-ready design. To make the design test ready, you need to fix violations; for example, Fixing Asynchronous Set and Reset Pin Violations. You can also run the DFT rule checker and fix the DFT Violations on a Scan-Mapped Design at any stage in the synthesis with DFT Flow.
To increase the coverage of your design, Insert Test Points Manually during synthesis.
You can also Insert Shadow Logic Around the Untestable Logic to increase the design’s controllability and observability.
To access the functional ports of your chip independent of system logic, Insert the Boundary Scan Architecture in your design.
You can also learn to add other test structures, such as Memory Built-In-Self-Test (MBIST) and Logic Built-In-Self-Test (LBIST). See our YouTube videos: What is MBIST and What is Logic BIST.

ATPG Flow with Modus DFT Software
Once your design is synthesized and includes the test architecture, you can seamlessly handoff to the Cadence Modus DFT Software solution to run the Automatic Test Pattern Generation ATPG flow. See the following steps and embedded links to the respective topics:

To understand Modus ATPG Flow Steps and its Graphical User Interface, watch the embedded video.
The first step is creating a Modus model, defined by Build Model. It does this by reading the design netlist and reading the structural library files combining together to create a design image. This model will be used for all further steps in the ATPG flow.
You can also build the test mode to set up the device for testing, as described in: What Is Test Mode.
To update the global fault list faults detected in the design, watch the video: What Is the Commit Experiment?
If you are curious about writing the industry standard test vector, click on the embedded link and watch the video ATPG Vector Generation and Writing the Patterns.
You can also debug the broken scan chains in your design by Debugging Broken Scan Chains using the Modus GUI or How to Debug Broken Scan Chains using Tcl Interface in Modus DFT?

Diagnostics with Modus DFT Software
Once your test patterns are generated, the real challenge begins—diagnosing manufacturing defects and identifying faults. Modus Diagnostics assists in identifying the root causes of defects in manufactured digital semiconductor devices.

Identifying the root cause facilitates corrective actions to avoid future defects and improve product yields. The Modus Test Diagnostics Overview is a good resource to start with.
Because there is no industry standard, failures from Automated Test Equipment (ATE) are reported in a variety of ASCII formats. You can convert your Tester Fail Data to Chip Pad Pattern CPP Format.
Modus has established a simple input Failure Format Called Chip Pad Pattern (CPP) file.
Once you Read the Tester Failure Data into binary format, you start diagnosing the failures in your design.
With Modus diagnostics capabilities, you can Diagnose Single/Multiple Manufacturing Defects in the functional logic of the chip, select all the faults in the logic back cone of the flops, then perform fault simulation and compare the results.
Modus DFT Software provides a wrapper that allows you to execute all steps, including determining if the failures are on Logic or Scan patterns, in one command. You can get more information by watching this Demo.

For more such videos and training bytes, login to Cadence Learning and Support Portal.

For technical shorts, subscribe to Cadence's official YouTube Channel

Boost Design Productivity by Cadence Digital Tools: Webinar Recording Available!

2026-07-02T03:30:00Z

This webinar series delivers practical methodologies and tool insights to help digital designers keep pace with growing complexity and meet aggressive tape out schedules with confidence. (read more)

Mastering Advanced Debug in Conformal LEC: Mapping to AI Driven Abort Resolution

2026-07-01T04:53:00Z

This blogs provides a structured learning approach to Conformal LEC debug that combines mapping, systematic NEQ and abort analysis, and AI-driven automation to accelerate equivalence closure.(read more)

Smarter DFT Starts at RTL: A Deep Dive into Modern DFT Flows with Genus

2026-06-30T18:00:00Z

This blog showcases the benefits of integrating DFT features within the synthesis task to deliver early and physically aware test flows for better PPA, cleaner scan architectures, and faster convergence.(read more)

RTL Design Studio: Bridging RTL Design and Physical Implementation

2026-06-26T20:45:00Z

The blog introduces RTL Design Studio as a breakthrough solution that empowers engineers to identify and fix timing, congestion, power, and structural issues early—right at the RTL stage—eliminating costly iterations during physical implementation.(read more)

Low-Power Equivalence Checking in Modern SoC Flows

2026-06-26T20:30:00Z

Background: Why Low-Power Equivalence Checking?

In modern SoC design, advanced low-power techniques such as dynamic voltage and frequency scaling, fine-grained power gating, multiple voltage domains, and state retention introduce additional logic and complexity to the chip. Unified Power Format (UPF) or Common Power Format (CPF) files are used to capture the design's "power intent"—describing power domains, power states, special cells (isolation gates, level shifters, retention registers), and required supply conditions.

These power-intent files guide EDA tools to automatically insert low-power structures into the netlist during synthesis and implementation, ensuring that circuits can safely power down or change voltage levels while preserving data or clamping signals. While essential, this process transforms the netlist beyond the plain RTL behavior, raising the question: is the low-power-augmented gate-level design still functionally equivalent to the original RTL?

Traditional verification alone (e.g., simulating the design with power-emulation models) is insufficient to thoroughly validate low-power behavior. Full-chip gate-level simulations with power shut-off scenarios are extremely slow and often impractical for large designs. Instead, formal equivalence checking augmented for low power provides an exhaustive and faster approach.

Cadence's solution—Conformal Low Power (CLP)—addresses this need by performing static structural and functional checks specifically for power-managed designs. It verifies that the power intent (from UPF/CPF) is correctly implemented and that no erroneous logic or mismatches have been introduced by adding power controllers and low-power cells.

In general, LPEC tools like Cadence Conformal Low Power solve two key problems in modern flows: firstly, checking direct equivalence between a golden design (RTL or pre-power-optimized netlist) and a revised netlist that includes all power-management modifications (power-gating logic, inserted isolation/level shifter cells, etc.). This power-aware equivalence checking ensures the design's functional behavior remains unchanged in active (powered-up) states. Secondly, Conformal Low Power performs static rule checks to flag structural issues, such as missing or incorrectly connected isolation cells or retention control pins, as well as any inconsistencies between the power intent specification and the design implementation. By catching these errors early, Conformal Low Power reduces the risk of latent low-power bugs causing functional failures or silicon respins.

Cadence Low-Power Equivalence Checking Solution

LP Verify — Static Signoff Checks: 600+ static LP checks from RTL through P&R, electrical/leakage checks for LP cells, power-intent quality/syntax validation, advanced LP cell support, and Tcl waiver/filtering.
LP Compare — Two-Design Consistency: Power intent, power grid/supply set, PST, crossing, and Liberty-vs-UPF consistency comparisons.
LP-EC — Power-Aware Equivalence: Logic equivalence with virtual ISO insertion, ISO/RET/PSW control signal comparison, virtual logic connection per power intent, and PSW acknowledge signal checks.

Usage of Cadence LPEC

Many semiconductor teams utilize Cadence's low-power equivalence checking at critical verification milestones.

A common practice is to run Conformal Low Power at the end of the design flow as part of final verification signoff, comparing the fully implemented gate-level netlist (with inserted power-management logic) against a golden RTL or gate-level model without those power optimizations.

By doing so as a mandatory step before tapeout, teams catch any inadvertent functional divergences caused by low-power structures that might not have been caught during standard verification.

This signoff usage aligns with industry recognition that low-power verification needs a formal signoff step similar to timing or functional signoff.

However, more advanced users incorporate Conformal Low Power earlier in the flow as well, rather than waiting until the very end.

Mature flows use CLP at multiple design stages (pre-synthesis, post-synthesis, and post-layout) as a layered defense against low-power bugs.

Customers also leverage CLP's diagnostics to debug issues when an equivalence mismatch is found.

What Is Lacking in Current Low-Power Verification Processes

Despite the availability of static low-power verification tools like Conformal Low Power, many teams do not fully exploit them. Common gaps observed in current customer processes include:

Applying low-power equivalence checking late in the flow rather than progressively. Many projects only run Conformal Low Power as a final step. This means if a logic bug was introduced by power optimizations (for example, an isolation cell clamping a signal erroneously), it may only be caught at the very end, causing late rework. Without early checks, some low-power mistakes remain hidden until final signoff.
Limited coverage of power modes and corner cases. Often the formal equivalence checks are done only for the "all power domains on" state (to ensure the active-mode logic is preserved), but not all combinations of power states are considered. Some flows may not verify behaviors during transitions (powering domains on/off) except via simulation, which might not exhaustively cover all sequences. These coverage gaps leave risk that certain power-down modes or recovery sequences aren't fully validated.

Recommended Improvements to LPEC Methodology

To address the above gaps, the following improvements are recommended for teams using Cadence's low-power equivalence checking. These suggestions aim to ensure more thorough coverage, earlier bug detection, and smoother integration of CLP into the overall verification process:

Incorporate CLP at multiple stages of the design flow: Run an initial static power intent consistency check once the UPF/CPF is written (to preempt structural mistakes).
Perform an RTL-to-synthesis equivalence check after logic synthesis and after insertion of low-power structures, rather than waiting till the end.
Finally, perform full-chip CLP at P&R signoff as a last line of defense. This multi-pass approach catches issues as early as possible, when fixes are less disruptive.
Define metrics and a signoff checklist: Create explicit low-power verification signoff criteria. A structured checklist can formalize that the design has undergone thorough low-power verification before tape-out.

Utilize Unified User Interface for Fast Debug

Easy Diagnosis — LP Debug Manager, Power Intent Viewer, Domain Crossing Viewer, and PST Viewer for clear visualization.
100X+ faster PST analysis enables early-stage validation without a full netlist and supports AI diagnosis on project history.
Root Cause Analysis auto-groups related violations by common cause and suggests fix actions.
Multi-threading delivers scalable performance with minimal memory overhead.
Distributed hierarchical flows (top-down, bottom-up, block-in-SoC-context) match flat full-chip results with automatic CPU/machine partitioning.

Conclusion

By systematically applying low-power equivalence checking with Cadence Conformal Low Power throughout the design cycle, verification teams can significantly reduce the risk of power-related functional bugs reaching silicon. Conformal Low Power formal approach provides exhaustive coverage of low-power scenarios and catches subtle errors that might slip past simulation. While many customers already leverage CLP for signoff, expanding its use earlier and refining processes around it will improve coverage and confidence in low-power designs. The improvements outlined in this report—from early integration to explicit verification metrics—will help organizations achieve robust low-power signoff and ultimately contribute to first-pass silicon success for power-efficient SoCs.

What Changed in Your Design? Stop Guessing—Let Stylus Compare Show You

2026-06-24T12:27:00Z

The blog positions Stylus Compare as a key solution for fast, accurate design comparison across iterations, ECOs, and cross-tool analysis. (read more)

Digital Design

Beyond Moore's Law: Advances in Modern Semiconductor Design

The Shifting Landscape

Moore's Law and Its Limits

The Original Promise

The Slowdown Factors

Inverse Moore's Law and Yield Economics

Transistor Architecture Evolution

Planar MOSFET: Dominant through roughly the 28nm era

FinFET: Mainstream at advanced nodes through the 2010s and into the 2020s

GAAFET: Emerging in leading-edge production and expected to expand further

Manufacturing: FEOL, MOL, BEOL

The Fabless Revolution and Rising Design Costs

Chiplets and Heterogeneous Integration

UCIe: The Universal Die-to-Die Standard

High Bandwidth Memory: The AI Workhorse

The Road Ahead

Related Courses

Power Grid Verification Flow: A Methodology for High-Coverage Signoff

The PPA Grand Prix: Fine-Tuning Designs with Advanced Synthesis

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Related Blogs

Might of Design Exploration: Deep Dive of Exploration Techniques in Stratus HLS

Understanding Exploration Techniques

Synthesis Control Attributes

Synthesis Directives and Tcl Commands

Configurable I/O Interfaces

How to Use Compile-Time Configuration and Abstraction to Make a SystemC Design Adaptable Across Multiple Data Types

Exploring Using Pipelining Constraints

What Do the Pipelining Constraints Help Resolve?

Active Module Parameters

Stratus HLS Integrates with Cerebrus for Automated Exploration

How Is HLS Design Space Exploration Performed with Cerebrus Primitives?

Conclusion

Accelerate Design Signoff with the Updated Cadence Voltus Training Kit

Cadence RTL Design Studio: Built for the Full PPAC Journey

Why Is the Name Changing?

What It Does

The Bigger Picture

The Truth About Complete DFT Flow: What Most Engineers Miss

Boost Design Productivity by Cadence Digital Tools: Webinar Recording Available!

Mastering Advanced Debug in Conformal LEC: Mapping to AI Driven Abort Resolution

Smarter DFT Starts at RTL: A Deep Dive into Modern DFT Flows with Genus

RTL Design Studio: Bridging RTL Design and Physical Implementation

Low-Power Equivalence Checking in Modern SoC Flows

Background: Why Low-Power Equivalence Checking?

Cadence Low-Power Equivalence Checking Solution

Usage of Cadence LPEC

What Is Lacking in Current Low-Power Verification Processes

Recommended Improvements to LPEC Methodology

Utilize Unified User Interface for Fast Debug

Conclusion

What Changed in Your Design? Stop Guessing—Let Stylus Compare Show You