Digital Design

The Odyssey of a Great Floorplan

2026-08-13T04:21:00Z

With the recent release of The Odyssey, audiences are once again following an epic journey filled with planning, obstacles, course corrections, and ultimately reaching a destination through skill and perseverance. While the world of VLSI physical design may seem far removed from ancient Greek adventures, experienced implementation engineers know that creating a successful chip floorplan is an odyssey of its own.

Every successful design begins with a journey. Before routing can be completed, timing can be optimized, or silicon can be manufactured, engineers must first navigate a sequence of critical floorplanning decisions. Much like Odysseus charting a path home through uncharted waters, physical designers must carefully guide a design from a collection of logical elements into an implementation-ready layout.

In our Innovus Basic Floorplanning video series, we follow that journey step by step, showing how each milestone contributes to a successful destination.

Setting Sail: Bringing the Design into the Physical World

Every journey starts with preparation. For Odysseus, it was assembling ships and crews. For physical designers, it begins by bringing together the information needed to construct the design database.

The first stage of the floorplanning journey focuses on importing the design and establishing the environment that will support all subsequent implementation activities. Logical descriptions, technology information, and timing views come together to create a foundation upon which every later decision depends. Without this foundation, the voyage cannot begin.

Charting the Map: Defining the Territory

A voyager cannot navigate without a map. Similarly, a chip cannot be implemented without defining its physical boundaries.

The next step establishes the overall dimensions of the design and allocates space between the core logic and the outer boundaries. These decisions influence placement, routing resources, congestion behavior, and overall design efficiency. What may seem like simple geometric choices at this stage frequently have consequences that ripple throughout the remainder of the implementation. Just as a captain studies coastlines and distances before leaving port, designers must understand the terrain before proceeding.

Navigating Complex Landscapes

Not every journey follows a straight path. The route home in The Odyssey is filled with unusual islands, obstacles, and detours. Modern SoC floorplans face similar complexity.

Design teams often need to create regions, placement constraints, and specialized floorplan shapes that reflect architectural requirements. Some areas must remain isolated. Others require guidance to influence placement behavior. In increasingly sophisticated designs, even the shape of the floorplan itself may depart from a simple rectangle. These techniques help engineers shape the physical landscape before major design elements arrive.

Positioning the Giants

In every epic story, massive landmarks define the journey. In physical design, those landmarks are hard macros. Memories, IP blocks, and other large structures consume significant portions of the layout and strongly influence routing patterns. Their locations determine channel widths, congestion hotspots, and connectivity efficiency throughout the design.

Our videos explore both the strategic placement of these critical structures and the techniques used to refine their arrangement. Engineers learn how to organize large blocks, create orderly arrays, maintain spacing, and analyze connectivity between major design components. Getting macro placement right early often determines whether the remainder of the implementation journey proceeds smoothly or becomes a struggle against congestion and timing challenges.

Reading the Signs

Throughout The Odyssey, travelers continually assess their surroundings and adjust their course. Successful floorplanning requires the same mindset.

Once macros are positioned, designers must evaluate utilization levels and routing channels to identify warning signs before they become serious obstacles. Congestion issues discovered late in implementation can significantly impact schedule and quality. Early reporting and analysis provide valuable insight into the health of the floorplan and reveal whether corrective action is necessary.

Adjusting the Course

Even the best plans require refinement. As designers review utilization and routing characteristics, they often discover opportunities to improve channel widths or redistribute available space. Rather than rebuilding from scratch, floorplans can be resized and adjusted while preserving the work already completed. Like a navigator correcting course after encountering changing conditions at sea, engineers make targeted modifications that improve the likelihood of a successful implementation.

Building Safe Passageways

Odysseus avoided dangerous waters whenever possible. Physical designers create their own safe passageways through the use of placement restrictions, routing constraints, and protective regions around sensitive structures. These mechanisms help prevent overcrowding, preserve routing resources, and maintain design quality. They guide implementation tools toward more effective solutions while reducing the risk of congestion-related problems. Such safeguards become increasingly important as designs grow larger and more complex.

Automating the Wisdom of Experience

One hallmark of mature engineering methodologies is the ability to automate best practices.

Experienced floorplanning engineers recognize problematic regions, narrow channels, and placement concerns. Modern implementation tools can apply that expertise automatically by identifying troublesome areas and creating optimization structures where they are needed.

This capability helps transform a good floorplan into a great one while reducing manual effort and improving consistency across designs.

Powering the Voyage

No ship travels without energy. Likewise, no chip can function without a robust power delivery network.

The next phase of the journey focuses on constructing the infrastructure that distributes power throughout the design. Engineers establish power connectivity, create distribution structures, and build the framework that will ultimately support reliable operation.

A well-designed power network is often invisible to end users, yet it is every bit as essential as the hull of a ship crossing the sea.

Reaching Ithaca: Completing the Floorplan

In The Odyssey, the journey culminates with Odysseus finally reaching home after overcoming countless challenges. Floorplanning reaches a similar milestone when power connectivity is completed, standard-cell placement begins, design health checks are reviewed, and the implementation database is saved for the next stages of the flow.

At this point, the floorplan has evolved from an abstract concept into a carefully engineered physical foundation ready for optimization and routing.

Every Great Chip Has an Odyssey

The appeal of The Odyssey has endured for centuries because it captures a universal truth: meaningful achievements are rarely accomplished in a single step. Success comes from a sequence of decisions, adjustments, lessons learned, and steady progress toward a goal.

The same is true in physical design. A successful floorplan is not simply created. It is discovered through a journey that begins with understanding the design, continues with careful planning and analysis, and concludes with a robust foundation for implementation success.

Whether you're guiding a hero across the Mediterranean or guiding a billion-transistor design toward tapeout, the principle remains the same: The destination matters, but the journey is where excellence is built.

Start your own floorplan odyssey by watching the Innovus Basic Floorplanning video series.

The 0.1 ns Mistake That Delayed an Entire Chip!

2026-08-07T05:31:00Z

We’ve all been there. You wake up early, get ready on time, leave home exactly as planned, but suddenly there’s traffic, a long signal, or an unexpected roadblock. By the time you reach your destination, you’re late. Now imagine what your boss is saying, “You left on time, so why are you late?” The answer is simple—real life isn’t ideal

Believe it or not, digital chips face the same problem. Inside a chip, data travels from one flip-flop to another, guided by the clock. Ideally, everything may look perfect. But in reality, tiny manufacturing variations and clock path differences can delay the data just enough to cause timing failures.

That’s why engineers don’t rely on ideal calculations. They calculate the Minimum Clock Time Period using concepts such as is (On-Chip Variation) and CPPR (Common Path Pessimism Removal) to ensure the chip operates reliably in the real world. Let’s understand these concepts as simply as possible.

What Is the Minimum Clock Time Period?

Think of the clock as a school bell. A student (data) must finish one class and reach the next classroom before the next bell rings. If the next bell rings too early, the student is still walking—and that’s exactly what happens in a setup timing violation.

So, the minimum clock period is the smallest period that allows data to safely travel from one flip-flop to the next. The basic formula is extracted during the setup timing analysis. As basic example design is shown below:

But real chips are never ideal. That’s where OCV and CPPR come into the picture.

What Is OCV?

OCV (On-Chip Variation) accounts for real-life manufacturing variations. Some paths become slightly faster, while others become slower due to changes in process, voltage, and temperature. Instead of trusting ideal delays, STA adds margins to make timing analysis more realistic and reliable.

Minimum Clock Time Period with OCV

When OCV is applied, the following mathematical calculations change as shown in the equations below,

Here, we assume:

The launch clock is late
The data path is late
Capture clock is early

This creates the worst-case setup timing condition. The following two 1-minute shorts will explain the calculation in more detail.

Minimum Clock Period Calculation in Static Timing Analysis without OCV?

Minimum Clock Period Calculation in Static Timing Analysis with OCV?

Why Do We Need CPPR?

Sometimes, both launch and capture clocks share the same clock path. OCV incorrectly applies variation to this common path twice, making the timing report more pessimistic than reality. This is where CPPR (Common Path Pessimism Removal) helps. It removes the extra pessimism from the shared clock path, giving a more accurate setup slack.

Minimum Clock Time Period with OCV + CPPRs

The mathematical formula includes the CPPR in the calculation:

Since unnecessary pessimism (Common Path Pessimism) is removed, as shown in the equation above, the required clock period often becomes slightly smaller, and the timing results are closer to what the silicon will actually experience. This 1-minute short will explain things quickly.

Watch the Shorts, practice the formulas, and you’ll find these timing concepts much easier to remember. To learn more about shorts, you can find many such YouTube Shorts/videos under Customer Education – Shorts on various topics. You can subscribe to this channel for more information and daily videos/shorts updates.

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both "Blended" and "Live" training. Please reach out to Cadence Training for further information — Watch this video, and don't forget to obtain your Digital Badge after completing the training!

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Stop Coding RTL First - A Smarter Path to Hardware Design Using SystemC

2026-08-06T09:36:00Z

Modern hardware design keeps demanding more -- more speed to market, more flexibility to absorb late spec changes, more scalability across derivative products. Yet the traditional flow is still built around a hard split: algorithm designers work in one model, architects explore another, and RTL verification engineers build yet another from scratch once the "real" design begins. Every handoff between those models is a place where intent gets lost, assumptions get re-guessed, and bugs get reintroduced that the previous stage had already ruled out. We tolerate this not because it's efficient, but because it's familiar.

A unified SystemC model breaks that split by refusing to treat algorithm validation, architectural exploration, HLS input, and RTL verification as separate problems. They aren't – they are four views onto the same design intent and forcing that intent through four separate models is where most of the schedule risk actually lives.

What makes a single C/C++-based model capable of standing in for all four is that it captures the properties each stage cares about, in one place: parallelism, timing, communication, and bit-accurate behavior.

An architect exploring trade-offs and a verification engineer checking correctness are no longer working from different truths -- they're working from the same one, albeit at different points in its lifecycle. That's not just a productivity gain. It changes what's verifiable, and when.

The result of all this? You architect faster and iterate smarter.

Modern chip design is becoming too complex for lengthy manual RTL development alone. SystemC enables engineers to:

Explore multiple architectures quickly
Validate functionality earlier
Bridge software and hardware teams
Accelerate RTL generation through HLS tools
Focus on design decisions instead of syntax
Faster design cycles and better architectural decisions early in the flow allow you to optimize the design for targeted PPA.

Faster design cycles and better architectural decisions early in the flow allow you to optimize the design for targeted PPA.

Why SystemC?

You're comfortable with C/C++ but hardware design feels like a giant leap into RTL. Suddenly, you're dealing with clocks, signals, finite state machines, timing constraints, and thousands of lines of Verilog.

What if you could explore architectures, verify functionality, and move toward RTL using skills you already have? That's exactly where SystemC changes the game.

SystemC occupies a unique position in digital design, sitting at the intersection of software abstraction and hardware accuracy. It is not merely a programming language; it is a hardware modeling framework built on C++, incorporated with hardware behavior constructs that allow designers to describe behavior, architecture, communication, concurrency, and timing at multiple abstraction levels.

This makes it exceptionally suitable for High-Level Synthesis.

Training Overview - What You’ll Learn

This two-day training traverses SystemC fundamentals and gradually progresses toward architecture exploration, optimization, and synthesis concepts through guided explanations and hands-on labs.

You will gain familiarity with SystemC by:

Creating synthesizable SystemC designs from the ground up
Modeling complex hardware behavior with concurrency and hierarchy
Writing HLS-friendly code using hardware-aware SystemC techniques
Exploring performance, area, and throughput trade-offs through optimization
Building industry-standard communication interfaces and protocols
Developing the skills to verify, debug, and validate hardware designs
Applying everything in a complete FIR filter design and synthesis workflow

What Will You Build?

The training is not just theory—you’ll apply concepts through a FIR filter lab, where you:

Model the design in SystemC
Simulate and verify functionality
Run synthesis using Stratus HLS
Analyze generated RTL

Who Should Take This Course?

If you’re involved in hardware design at any level, this course is built for:

Hardware/software engineers
Design and system architects
Managers planning HLS-based projects

What Sets This Training Apart:

SystemC and High-Level Synthesis are increasingly used in:

AI accelerators
Imaging and vision systems
Networking hardware
Communication systems

Engineers who understand architectural modeling can evaluate design trade-offs much earlier in the development cycle:

Unified design flow: Helps you move seamlessly from high-level modeling to RTL without switching paradigms.
Architecture-centric thinking: Make informed decisions about performance, area, and throughput early in the design cycle.
Industry-relevant tools: Stratus HLS usage and exercise modern verification flows.
Reusable skills: Apply concepts across domains ranging from display processing units to communication systems.

Outcome

The future of hardware design isn't about writing RTL sooner. It's about making better architectural decisions sooner. If you're looking to bridge the gap between software thinking and hardware implementation, SystemC provides one of the most practical paths to get there.

This training helps you take that journey from your first SystemC model to hardware-ready designs and by the end of this course, you won’t just “write SystemC code”—you’ll be able to:

Transform algorithms into hardware-ready designs
Optimize designs using pipelining, parallelism, and architectural exploration
Build robust, scalable, and verifiable HLS-based solution

Where to Take the Training?

The training is available in two versions:

Live Training [Instructor-Led]: Please contact Cadence Training.
Online Training [Self-Learning]: Learn more about the online course on the Cadence ASK site.

Customers/learners will be presented with a badge exam after course completion, and upon successfully achieving the grade, the learner will earn a badge.

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What Next?

Explore deeper insights into Stratus HLS and digital design methodologies:

Enhance your expertise through the following relevant training:

What Is Accelerated Learning?

The faster you finish your online training, the sooner you can claim your Digital Badge. Want to know how accelerated learning works? Our video walks you through the pre-quiz, navigation, and essential features. We're regularly adding new Accelerated Learning titles.

Accelerated Learning courses are marked with this symbol in our Learning Maps.

Beyond Moore's Law: Advances in Modern Semiconductor Design

2026-08-01T00:45:00Z

The Shifting Landscape

For decades, Moore's Law delivered a simple promise: more transistors, more performance, and lower cost. Today, that equation is changing. As transistor scaling approaches physical and economic limits, innovation is shifting beyond the transistor itself—into advanced packaging, heterogeneous integration, chiplets, memory architectures, and system-level optimization.

This blog explores the major shifts shaping this transformation—from transistor architecture evolution and manufacturing complexity to chiplet-based design, UCIe standardization, and high-bandwidth memory.

Moore's Law and Its Limits

The Original Promise

Gordon Moore's 1965 observation originally described a doubling roughly every year; he later revised it in 1975 to roughly every two years. This exponential trajectory held remarkably true for decades:

Intel 4004 (1971): 2,300 transistors
Pentium (1993): 3.1 million transistors
Apple M1 Ultra: 114 billion transistors
NVIDIA Hopper: 80+ billion transistors

The Slowdown Factors

However, pure transistor scaling is no longer the whole story. Several forces are slowing traditional Moore's Law:

Physics limits: short-channel effects, leakage, and quantum-mechanical effects become more severe at advanced nodes.
Lithography complexity: increasing EUV process complexity and cost at advanced nodes
Economic pressure: leading-edge design and productization costs can reach extremely high levels, with advanced-node programs potentially exceeding $1B overall.
Power density: Dennard scaling ended circa 2006.

As a result, traditional scaling is no longer sufficient on its own.

Inverse Moore's Law and Yield Economics

Even as transistor scaling slows, the cost of delivering useful computing capability at the system level often continues to decline through architectural innovation, software optimization, and economies of scale, where the cost of delivering a given amount of functionality tends to fall over time. For example, systems that once cost millions are now consumer-grade products.

But at advanced nodes, yield economics become a major constraint:

Larger dies will have more defects leading to lower yield
Advanced nodes (3nm and below) result in exponentially higher cost per die.

This creates a critical challenge: Building larger monolithic chips is becoming economically unsustainable. This pressure drives the industry toward alternative design approaches.

Transistor Architecture Evolution

Planar MOSFET: Dominant through roughly the 28nm era

The workhorse of early semiconductor scaling. The gate sits on top of a flat channel, controlling current flow from above only. Simple and cost-effective at larger nodes, but as dimensions shrank below 28 nm, the gate lost adequate control over the channel, leading to unacceptable leakage currents.

FinFET: Mainstream at advanced nodes through the 2010s and into the 2020s

Intel introduced FinFETs at 22nm. The channel rises as a vertical "fin" with the gate wrapping around three sides, dramatically improving electrostatic control. This enabled scaling down to 5 nm with manageable leakage and better performance-per-watt. Fin height variability and patterning at tighter pitches are its key manufacturing challenges.

GAAFET: Emerging in leading-edge production and expected to expand further

Gate-All-Around FETs (nanosheets/nanowires) represent the frontier. The gate completely surrounds the channel, providing the strongest electrostatic control and the sharpest ON/OFF switching. Manufacturing requires selective layer deposition, channel release etching, and precise nanosheet thickness control—significantly more complex than FinFET fabrication.

These innovations extend Moore's Law, but at the cost of massive manufacturing complexity.

Manufacturing: FEOL, MOL, BEOL

Modern chip fabrication is divided into three precisely orchestrated stages, each building on the previous one.

The Fabless Revolution and Rising Design Costs

The semiconductor industry has undergone a fundamental structural transformation. As manufacturing complexity increases, so does cost. Where companies once designed and manufactured their own chips (IDM model), the prohibitive cost of modern fabs—often exceeding $10-20 billion has left only a small number of companies capable of operating leading-edge manufacturing facilities.

Today, leading-edge logic manufacturing is concentrated among Intel, TSMC, and Samsung.

This has fundamentally reshaped the industry.

Most other major semiconductor companies—Qualcomm, Broadcom, NVIDIA, and AMD—have transitioned to a fabless model, focusing on design while outsourcing manufacturing.

Meanwhile, IC design costs have skyrocketed. A typical chip costs $10-100M to design; a state-of-the-art microprocessor can exceed $1B. Verification can account for a significant majority of development effort in advanced SoC programs. Product revenues must be roughly 10X development costs to justify investment, creating intense pressure on first-time-right silicon.

These economic pressures demand new design methodologies.

Chiplets and Heterogeneous Integration

Instead of building a single 800 mm² die that may suffer from poor yield, manufacturers can construct a system from multiple smaller chiplets with higher individual yield and lower overall cost.

To address yield and cost challenges, the industry is moving toward building systems from multiple cooperating dies or chiplet-based architectures instead of one monolithic chip.

Chiplets

2.5D vs 3D Integration

Smaller functional dies that together form a complete system. Each chiplet implements a specific function—compute (CPU/GPU/AI), memory, IO/SerDes, or accelerators.

Key advantages:

Higher individual yield per die
Reuse across product lines
Mix-and-match process nodes (3nm + 7nm + 28nm)
Only known-good dies assembled

2.5D: Side-by-side dies on an interposer with fine-pitch routing. Better heat spreading, predictable power delivery. Ideal for logic + HBM configurations.

3D: Vertical die stacking connected via Through-Silicon Vias (TSVs) or hybrid bonding. Extremely high bandwidth and density, but poses thermal challenges as upper dies trap heat. Maximum density for memory stacks.

Chiplets mark a shift toward system-level design instead of single-chip scaling.

UCIe: The Universal Die-to-Die Standard

As chiplet adoption grows, a new challenge emerges: How do chiplets from different vendors communicate? Without standardization, proprietary interfaces limit ecosystem growth.

UCIe has the potential to do for chiplets what PCI Express did for expansion cards -create an open ecosystem where components from different vendors can interoperate through a common interface.

Universal Chiplet Interconnect Express (UCIe) is the industry's answer—an open standard that defines high-bandwidth, low-latency, power-efficient die-to-die communication inside a single package.

Interoperability	Reuse and Scale	Performance	Simplified EDA
Build systems from a multi-vendor chiplet ecosystem	Faster time-to-market, lower design risk	High-performance multi-die systems at package scale	Standardized signoff for die-to-die interfaces

UCIe transforms chiplets into a true modular ecosystem.

These system-level innovations introduce new verification, implementation, and signoff challenges. Engineers must now validate multi-die connectivity, advanced package interactions, thermal behavior, power integrity, and chiplet interoperability. As a result, EDA flows are expanding beyond traditional SoC implementation into system-level design and analysis.

High Bandwidth Memory: The AI Workhorse

Many AI and HPC workloads are fundamentally memory-bandwidth limited, rather than purely compute-limited.

In modern AI accelerators, compute resources often sit idle while waiting for data. HBM addresses this bottleneck by dramatically increasing memory bandwidth, allowing GPUs and AI processors to remain fully utilized.

How HBM solves this:

Multiple DRAM dies stacked vertically
Through-silicon vias (TSVs) for vertical connections
Silicon interposer for dense die-to-processor wiring
Short, fast data paths to the GPU/AI accelerator

HBM provides:

High bandwidth and energy-efficient data movement
Latency benefits depend on system architecture and access pattern

HBM in modern systems:

Requires advanced 2.5D/3D packaging
Tightly coupling memory with GPUs/AI accelerators within a single package
Short data paths for faster access

The Road Ahead

The future of semiconductor innovation will not be defined by transistor scaling alone. Success increasingly depends on how effectively designers integrate advanced process technologies, packaging, memory, interconnects, and software into complete systems.

Moore's Law was never just about shrinking transistors—it was about continuous progress in performance, cost, and capability.

That progress continues, but through a different paradigm:

GAAFETs pushing transistor scaling further
Chiplets overcoming yield and cost barriers
UCIe enabling ecosystem-level integration
HBM delivering the bandwidth that AI demands

In the Beyond-Moore era, the package is becoming the new system, and system-level optimization is becoming the new scaling strategy.

To learn more about advanced semiconductor topics, enroll in our Semiconductor 101 v3.0 training and earn a Cadence Digital Badge.

To learn about other courses, see the Learning Map and take training courses in different areas of chip design based on your interests.

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Power Grid Verification Flow: A Methodology for High-Coverage Signoff

2026-07-31T16:30:00Z

As semiconductor designs continue to scale in complexity, ensuring robust power integrity becomes one of the most important challenges in design signoff. Power grid weaknesses can appear as IR drop violations, excessive supply noise, timing degradati...(read more)

The PPA Grand Prix: Fine-Tuning Designs with Advanced Synthesis

2026-07-30T12:30:00Z

Ever watched a Formula One race and wondered what makes the winning car just a little faster than the rest?

It's rarely one big breakthrough.

It's hundreds of tiny optimizations working together—better aerodynamics, smarter tire strategy, precise tuning, and countless engineering decisions made behind the scenes. The difference between first place and the pack is often measured in milliseconds.

Advanced synthesis is no different.

Achieving the best power, performance, and area (PPA) requires far more than pressing "Run." It requires understanding how to fine-tune constraints, guide optimization strategies, leverage physical awareness, analyze timing bottlenecks, and make informed trade-offs throughout the flow.

Every picosecond recovered, every microwatt saved, and every area improvement gained is another advantage in the race toward design closure.

And let's be honest—if you've ever spent hours tweaking constraints to recover a few picoseconds, you've already discovered that synthesis engineers and Formula One teams share the same obsession: celebrating incredibly small numbers that somehow make a huge difference.

That's where the Advanced Synthesis with Genus Stylus Common UI training comes in.

Online Link:

Designed for engineers ready to move beyond the fundamentals, this course helps you transition from simply running synthesis to understanding and influencing the optimization decisions that drive superior QoR.

Elevate your skills with advanced synthesis techniques to optimize PPA results and ensure alignment with place and route processes. The training guides debugging issues in complex design synthesis, focusing on timing, area, and power optimization. It includes example problem scenarios commonly encountered in synthesis flows and offers strategies for effective debugging.

Because in today's design challenges, success isn't just about finishing the race.

It's about engineering every possible advantage before the green flag drops

Hands-on Learning with Labs and Training Bytes

To reinforce theoretical knowledge, the training includes:

Labs: To facilitate a seamless learning experience, we provide hands-on labs encompassing various design scenarios.

The training and lab exercises are specifically designed to help you reach your objectives, with step-by-step lab instructions conveniently available in the interactive lab book.

Lab Videos: Here's where it gets exciting!"

We provide dynamic video content for each training lab to support your learning journey. Every lab module includes a demo-style walkthrough of the instructions, making it easier to ramp up the tools and troubleshoot any steps. Whether you're just a beginner in synthesis or already have some experience, we're here to help you navigate it confidently.

Kickstart your journey to becoming a synthesis expert with our captivating series of short lab videos, now available on the ASK site.

Demo: Analyze, Synthesize, and Optimize the design for the best possible timing with the Genus Synthesis Solution (Video)

What's Next?

Grab your Digital Badge after finishing the training and flaunt what expertise you have built up.

This is something you'll actually want to show people.

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

As a next step, you can further leverage the vast database of videos and detailed training on Cadence Application Support and Knowledge Portal (Cadence login required).

Bonus Features

Enhance the Genus Synthesis Solution experience with short videos: Genus Synthesis Solution: Video Library.
Get ready for the most thrilling experience with Accelerated Learning!
Did you already know?

The Cadence YouTube channel hosts a Customer Education Training Bytes channel.

The latest trendy channel is Customer Education – Shorts - YouTube, where you can view a variety of training bytes for which you do not need a Cadence ASK account.

Bite-Sized Learning for Big SoC Challenges: Genus Training Bytes - Digital Design - Cadence Blogs - Cadence Community

Your Skills Deserve a Passport: Showcase Your Expertise with Digital Badges - Digital Design - Cadence Blogs - Cadence Community

Modular Magic: Accelerate Chip Design with Genus Bottom-Up Flows - Digital Design - Cadence Blogs - Cadence Community

From Chaos to Clarity: Mastering PBS MiM Flow Without the Land Disputes - Digital Design - Cadence Blogs - Cadence Community

Your Phone Gets Updates, So Does Your Synthesis Expertise!

2026-07-28T04:54:00Z

Most of us update our phones without ever knowing about the coolest new features hidden inside. The same can happen with synthesis tools—powerful capabilities get added, but they often remain undiscovered.

That's why we've created a new set of Genus Training Bytes: quick, easy-to-digest videos that reveal some of the latest enhancements and innovations without requiring you to dive into lengthy documentation.

Featured Training Bytes

🔹 Clock Gating History Recording – Gain visibility into clock-gating decisions and simplify debug of gated and ungated flops

🔹 What Is Common Front End (CFE)? – Learn how a unified RTL processing framework enables more consistent and powerful optimizations across the digital implementation flow.

🔹 Improvements in Handling Constant Flops – Explore enhancements that help identify and optimize more constant sequential logic.

🔹 What Is Cut-Based Mapping? – Discover an advanced logic-mapping technique that improves technology mapping efficiency and quality of results.

🔹 Commands and Attributes to Control Partition-Based Synthesis Multiple Instantiated Modules (PBS MiM) Flow – Understand the controls available for optimizing synthesis of highly repetitive designs.

🔹 What Is Advanced Structuring? – See how advanced logic restructuring techniques help improve PPA through sophisticated optimization strategies.

Start Learning Today

Don't let great features stay hidden. Explore the latest Genus Training Bytes and unlock what's already waiting in your toolbox.

Watch the latest Training Bytes and accelerate your understanding of the newest Genus capabilities:

Clock Gating History Recording (Video)

What Is Common Front End (CFE)? (Video)

Improvements in Handling Constant Flops (Video)

What Is Cut-Based Matching? (Video)

Commands And Attributes To Control PBS MiM Flow (Video)

What Is Advanced Structuring? (Video)

What Else Can You Explore at the ASK Portal?

Free Online Trainings: The Online Trainings are free for all Cadence customers with a Cadence ASK Account. For instructor-led training sessions, "Live" or "Blended," please contact Cadence Training.

Further enhance the Genus Synthesis Solution learning experience with short videos: Genus Synthesis Solution: Video Library.
Did you already know?

The Cadence YouTube channel hosts a Customer Education Training Bytes channel.

The latest trendy channel is Customer Education – Shorts - YouTube, where you can view a variety of training bytes for which you do not need a Cadence ASK account.

Bite-Sized Learning for Big SoC Challenges: Genus Training Bytes - Digital Design - Cadence Blogs - Cadence Community

Your Skills Deserve a Passport: Showcase Your Expertise with Digital Badges - Digital Design - Cadence Blogs - Cadence Community

Modular Magic: Accelerate Chip Design with Genus Bottom-Up Flows - Digital Design - Cadence Blogs - Cadence Community

From Chaos to Clarity: Mastering PBS MiM Flow Without the Land Disputes - Digital Design - Cadence Blogs - Cadence Community

Still Using Synthesis Tricks from Your "Golden Script" Folder? Consider Upgrade!

2026-07-23T05:39:00Z

Ever looked at an old synthesis script and thought, “Who wrote this masterpiece of confusion?” Then realized… It was you. Six months ago. You're not alone.

Every engineer has one. That mysterious folder containing TCL scripts copied from project to project, generation after generation. Nobody remembers who created them. Nobody wants to modify them. And somehow they're still running.

When a new project begins, the ritual is familiar:

"Copy the scripts."

"Update a few paths."

"Hope for the best."

While legendary scripts deserve respect, modern SoC designs have evolved significantly. Timing targets are tighter, power goals are more aggressive, and design complexity continues to grow. Successfully achieving the best Power, Performance, and Area (PPA) requires more than relying on yesterday's synthesis habits—it requires understanding today's synthesis capabilities and methodologies. The Genus Synthesis Solution is designed to help deliver optimal productivity and PPA during RTL synthesis.

Because sometimes the best optimization isn't another synthesis run. It's upgrading the synthesis knowledge! That's where the Genus Synthesis Solution with Stylus Common UI training comes in.

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Whether you're new to synthesis or a seasoned designer looking to refresh your expertise, this course helps you move beyond inherited scripts and develop a deeper understanding of the Genus synthesis flow, modern optimization techniques, and debugging strategies needed for today's complex designs. The training covers design constraints, timing analysis, physical synthesis, low-power optimization, DFT constraints, and complete synthesis flow execution to optimize area, timing, and power.

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How to Run the Setup for Synthesis, Load Libraries, and Design And Elaborate The Design Module in Genus Synthesis Solution? (Video)

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Might of Design Exploration: Deep Dive of Exploration Techniques in Stratus HLS

2026-07-22T09:49:00Z

Stratus HLS's behavioral design methodology enables easy exploration of multiple algorithms and architectures to achieve better trade-offs among area, power, and latency requirements.

In this blog, we'll delve into the various exploration techniques that Stratus HLS provides and how they can revolutionize your design process.

Understanding Exploration Techniques

Exploration techniques in Stratus HLS primarily focus on evaluating microarchitecture decisions as the design evolves, considering trade-offs to produce different solutions. Stratus HLS determines the behavior of a synthesized design from the SystemC source, but there are many ways to transform the same SystemC into RTL.

Microarchitecture control is how you influence that transformation without changing the source code.

The microarchitecture is controlled by three mechanisms, which can be used independently or together:

Synthesis control attributes
Synthesis directives and Tcl commands
Active module parameters
A fourth dimension is configurable I/O interfaces that are managed separately through io_config and the generated Interface library, and controls what the module's ports look like at each abstraction level. A configurable system model enables trade-offs between protocols and data types without modifying the core design.

Let us further explore how to apply these mechanisms.

Synthesis Control Attributes

Synthesis control attributes affect synthesis decisions globally or individually for each hls_config. As tabulated here, there are three different ways to set the synthesis attributes:

Scope	Method of Setting	Example
Project-wide (All configs)	set_attr <outside any config block>	set_attr clock_period 7.5
Per hls_config	--attr = value on define_hls_config	--sched_asap=on
Batch across multiple configs	set_attr with find	set_attr cycle_slack 1.2 [find -hls_config <configName>]

Any typical exploration pattern defines a family of configs, then differentiates them. The most frequently used configs are, hls_config, sim_config, analysis_config, cov_config, equiv_config, io_config, logic_synthesis_config, power_config, sim_config, system_config.

These basic setup parameters help in exploring how timing, pipelining, and memory organization interact to shape the final RTL architecture.

Setting the stage for the HLS: The synthesis setup begins by defining a clock period and a default input delay, thereby establishing the effective timing budget available for internal scheduling and datapath generation.
- set_attr clock_period 5
- set_attr default_input_delay 1.5

Defining multiple HLS configurations for exploration: This is a classic design-space exploration setup: same functionality, different synthesis strategies. To explore multiple implementation styles of the same design, in this example, four HLS configurations — BASIC1, FLATTEN, UNROLL, and DPOPT are created.
- define_hls_config dut BASIC
- define_hls_config dut FLATTEN -- flatten_arrays=all
- define_hls_config dut UNROLL -- unroll_loops=on
- define_hls_config dut DPOPT -- dpopt_auto=all

Other attributes: Multiple such attributes are available in a structured manner to tune the design for better and a balanced tradeoff between area, performance, and timing closure
- set_attr flatten_arrays all [find -hls_config FLATTEN*]
- set_attr cycle_slack 2 [find -hls_config *]

The clock period is a primary timing knob used to define the target cycle time for scheduling and datapath synthesis. To go beyond the basic clock setting, Stratus provides additional tuning knobs. These parameters determine how aggressively your logic can be packed, and this flexibility enables you to make your design more or less aggressive in packing logic into clock cycles, ultimately impacting latency, timing closure, and a balanced QoR.

cycle_slack: Specifies an amount of time in each clock period that is to be reserved for use by downstream tools.
path_delay_limit: Specifies a variable upper bound of the allowable length of timing paths, true or false, in your design

Here is the differentiation of a design with the application of slack or no slack:

No Slack	With Slack
Faster Parts	Smaller Parts
More Registers	Fewer Registers
Higher Area	Better QoR balance

When timing cannot be met, StratusHLS reports scheduling failures, Loop Carried Dependency [LCD] violations, and resource conflicts. By setting latency constraints, you can explore the impact of different latency values on your design's performance and area. It is important to note that the latency constraints are a major cause of scheduling failure.

Common causes include data dependencies, insufficient operator timing, conflicting protocol boundaries, resource conflicts, and incompatible loop-carried dependencies. When this occurs, Stratus HLS reports minimum achievable latency, and error diagnostics identify blocking constraints. Latency constraints in Stratus HLS specify the maximum number of cycles a region is allowed to consume, guiding the scheduler’s trade-offs among parallelism, resource usage, and performance.

In summary,

Tighter latency ⇒ More parallel hardware, less sharing.
Looser latency ⇒ Serialized execution, reduced area.

Synthesis Directives and Tcl Commands

Directives and Tcl commands target specific objects in the source: loops, arrays, regions, and ports. They are the mechanism for fine-grained microarchitecture control. In HLS, elaboration is the stage where the design hierarchy, loops, variables, interfaces, and internal structures are fully understood by the tool.

When to use:

Use synthesis directives when you are working with the source code. Let us see an illustration of the usage as a source directive in the code.
while (1){

HLS_PIPELINE_LOOP (HARD_STALL, 1, "MAIN_LOOP");

vin = din.get();

vout = f( vin );

dout.put( vout ); }
Use Tcl commands, when keeping synthesis policy separate from behavioral specification, or when you need to vary the policy per hls_config.

In the project file:

define_post_elab_tcl {

pipeline_loops -type HARD_STALL -initiation_interval 1 [find -loop MAIN_LOOP] }

In the source code:

MAIN_LOOP: while (1){

vin=din.get(); vout=f(vin); dout.put(vout);}

Several synthesis directives and their equivalent TCL commands are available. You can refer to the HLS reference guide for further information on these.

Directive Name	Effects
HLS_UNROLL_LOOP	Unrolls iterations; Increases parallelism; Trades area for latency
HLS_PIPELINE_LOOP	Pipelines the loop; Overlaps iterations; Trades area for throughput
HLS_CONSTRAIN_LATENCY	Constrains cycle count; Forces parallelism or serialization
HLS_FLATTEN_ARRAY	Forces array to individual scalar registers, enabling parallel access.
HLS_MAP_TO_REG	Maps an array to registers
HLS_MAP_TO_MEMORY	Maps an array to a named memory instance
HLS_BREAK_PROTOCOL	Insert a cycle boundary at a specific protocol point.
HLS_DPOPT_REGION	Applies data path optimization to the enclosed arithmetic

The table lists several key directives and their microarchitectural effects.

Configurable I/O Interfaces

In High-Level Synthesis, your algorithm stays the same, but the way it talks to the outside world is completely configurable. Configurable I/O interfaces are managed separately from the microarchitecture controls above.

If you need,

Low latency? Use direct IO.
Safe communication? Add a handshake.
Processing large data? Go memory or streaming.

This means the same design can plug into completely different systems just by changing the interface configuration. You can control the abstraction level and protocol of the module's ports without changing the DUT or testbench code.

Stratus HLS introduces the following interface types to optimize your design.

An ‘io_config’ to control which ports and channels are used to connect modules in the system.
There are predefined i/o configs:
- PIN Level: Pin-accurate protocol; synthesizable; cycle-accurate
- TLM: Transaction-level modeling; loosely timed; faster simulation
An interface generator (bdw_ifgen) that produces C++ interface classes from interface definitions (.bdl files).

How to Use Compile-Time Configuration and Abstraction to Make a SystemC Design Adaptable Across Multiple Data Types

In SystemC-based HLS flows, developers often work with multiple numeric types such as sc_int, sc_bigint, and ac_int. Each has different precision capabilities, performance implications, and synthesis characteristics. Without abstraction, switching between these types means rewriting large portions of code.

Data types in the source code - defines.h;

Data types in the source code - file.h;

Data types in the source code - file.cpp

The image depicts the way of configuring the design interfaces for the above-defined data types

Exploring Using Pipelining Constraints

Pipelining constraints are one of the primary exploration axes in Stratus HLS because they directly trade off throughput vs. area, latency, resource sharing, and clock frequency feasibility. Through pipelining, Stratus HLS allows designers to generate multiple microarchitectures from the same source code, where a single untimed algorithm can yield multiple microarchitectures, each with vastly different performance and cost, simply by tuning pipelining.

What Do the Pipelining Constraints Help Resolve?

When pipeline constraints are applied, Stratus HLS may report that a requested initiation interval is not achievable, that Loop-carried dependencies prevent pipelining, or that resource or memory conflicts stall the pipeline.

These reports help identify and, in turn, resolve:

Algorithmic bottlenecks
Refine pipeline constraints
Adjust loop structure or memory layout

Applying pipelining constraints transforms sequential algorithms into high-performance hardware pipelines while allowing designers to navigate a wide design space using Initiation Interval, Stall modes, as prime parameters.

The image indicates the area numbers for different configurations.

Active Module Parameters

Active module parameters are a configuration-level abstraction. It does not require any Tcl scripts or source directives. Internally, these parameters translate into synthesis directives at post-elaboration. For training and design-space exploration, Active Module Parameters are particularly valuable because they let you create configuration variants, all without touching the source code.

Active module parameters are specified in define_hls_config using forms such as:

-parameter = value
-parameter:object = value

These parameters execute Tcl bodies that generate the underlying Stratus directives automatically. Example usage of the parameters is as shown:

define_hls_config mymod CFG1 -main_latency=10
define_hls_config mymod CFG2 -pipeline_loop:my_loop=1

Here is the table listing the parameters that allow you to steer the micro‑architecture without rewriting the source code — shifting your role from coder → architect.

Design Intent	Parameter	Controls
Latency Control	-main_latency, -constrain_latency: <loop>	Controls total execution cycles of function/loop
Loop Pipelining	-main_pipeline, -pipeline_loop:<loop>	Enables overlapping execution of loop iterations
Data Path Optimization	-dpopt_region:<region>, -dpopt_function:<fn>	Optimizes operator sharing, restructuring, and logic mapping
Memory vs Register Mapping	-map_array:<array>	Chooses how arrays map to hardware: RAM / Registers / Flattened

Stratus HLS Integrates with Cerebrus for Automated Exploration

Cadence Cerebrus is a design optimization tool that applies machine learning (ML) to achieve optimal PPA. When applied to Stratus HLS, the goal is to produce the optimal RTL from a behavioral model rather than to optimize a fixed RTL. The Stratus-Cerebrus integration automates exploration and guides it with ML to converge on an optimal result.

Cerebrus is configured with a set of primitives that define the space to be explored and a cost function that determines how PPA will be evaluated. Based on the metrics and primitives set for those scenarios, Cerebrus learns which primitives move the results closer to an optimal target. Cerebrus further explores the values of the enabled primitives and seeks the set that yields the best PPA. Stratus HLS provides utilities for specifying project primitives.

The image illustrates the power of using Cerebrus to explore a design.

How Is HLS Design Space Exploration Performed with Cerebrus Primitives?

HLS is not just about writing SystemC code, but about exploring architectural choices intelligently. And Cerebrus is used in Stratus HLS to accelerate the production of the optimal RTL, rather than to optimize a particular RTL. The flow begins with an hls_config that successfully produces RTL, but that does not yet yield optimal PPA. Here are the key advantages of using Cerebrus for exploration:

No code changes required
- All design exploration is controlled externally via Cerebrus scripts
- The original SystemC/HLS design remains untouched
Exploration-driven optimization
- Each setup defines a search space of architectural and synthesis choices
- Includes constraints and goals for PPA evaluation
Automated iterative flow
- Cerebrus repeatedly runs the Stratus HLS synthesis flow
- Automatically adjusts configurations between runs to explore better solutions
Scenario-based exploration
- Each combination of settings creates a unique design scenario
- These scenarios are stored as hls_configs in the Stratus database
Seamless integration with Stratus
- Generated scenarios behave like standard HLS configurations
- Can be further analyzed using the Stratus IDE
Real-time tracking and analysis
- Cerebrus UI provides visibility into:
  - Exploration progress
  - Scenario completion status
  - Comparative evaluation of results

This image illustrates the typical inputs known as primitives in Cerebrus. The details defined by the "max_scenarios" option in the init_cerebrus script help in exploring the design, including the other parameters.

This is design space exploration for multiple combinations of timing constraints, scheduling strategies, and resource optimizations automatically explored by Cerebrus. Instead of manual tuning, exploration is automated, and the design space is covered efficiently, leading to faster identification of optimal architecture.

This image depicts the five design exploration scenarios (scenario_1 → scenario_5) evaluated against a base configuration.

Cerebrus rapidly explores multiple HLS optimization strategies and automatically converges on configurations delivering ~25% better QoR without increasing runtime.

The images show the results indicating the best design, enabling optimal tradeoff decisions

Conclusion

Stratus HLS is a game-changer in the world of digital design. The exploration techniques provide unparalleled flexibility and control, allowing you to optimize your designs for area, performance, and power. Exploration is achieved by defining multiple hls_config and systematically varying synthesis attributes, directives, scheduling contexts, datapath partitions, interfaces, and parameters, manually or via Cerebrus, to analyze and compare QoR trade-offs.

Explore deeper insights into Stratus HLS and digital design methodologies:

Stratus HLS - Digital Design - Cadence Blogs - Cadence Community

Enhance your expertise through the following relevant training:

SystemC for High-Level Synthesis Training Course

Stratus-HLS Basic Training

Cadence Cerebrus Intelligent Chip Explorer

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Accelerate Design Signoff with the Updated Cadence Voltus Training Kit

2026-07-21T03:44:00Z

By Ronen Stilkol, Senior AE Architect As advanced-node and 3D-IC designs push higher performance into tighter power, thermal, and packaging constraints, engineers must understand how the die, package, board, activity profile, and implementation flow ...(read more)

Cadence RTL Design Studio: Built for the Full PPAC Journey

2026-07-14T17:00:00Z

If you've used Joules RTL Design Studio, you already know what it can do. Now it has a name that matches its full potential.

We're renaming Joules RTL Design Studio to Cadence RTL Design Studio. The product isn't changing, just the name.

Why Is the Name Changing?

When Joules RTL Design Studio launched, it expanded upon the Joules RTL Power Solution by adding visibility into performance, area, and congestion alongside power. But the "Joules" name stuck—and with it, the perception that this was primarily a power tool. It isn't. It never was just power.

Cadence RTL Design Studio is a full PPAC solution. It gives front-end designers early, accurate insight into power, performance, area, and congestion—all before handoff to implementation. The new name makes that clear from the get-go.

What It Does

Cadence RTL Design Studio delivers up to 5X faster RTL convergence and up to 25% improvement in quality of results (QoR) by bringing physical design feedback to the RTL stage—where changes are fastest and cheapest to make.

Key capabilities include:

Full PPAC visibility at RTL – Identify timing, congestion, power, and area issues early, before they become costly implementation problems.
Intelligent RTL debugging assistant – An expert system that triages violations, explores what-if scenarios, and provides actionable guidance to resolve issues directly in the source code.
Proven engine accuracy – PPAC estimates are driven by the same trusted engines as Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, so designers can trust that RTL-stage decisions will track with production implementation.
Unified cockpit – A single GUI for RTL analysis, schematic cross-probing, layout feedback, and design exploration.
AI-powered design exploration – Integration with Cadence Cerebrus^® Intelligent Chip Explorer enables generative AI-driven exploration of floorplan optimization, frequency vs. voltage tradeoffs, and more.
Prototyping support – Designers can explore and prototype design decisions prior to committing to place and route, reducing costly late-stage iterations.

The Bigger Picture

For too long, RTL designers operated separately from implementation engineers. Problems that could have been identified and resolved quickly during the RTL phase were instead found later, causing costly revisions and delaying product release.

Cadence RTL Design Studio closes that gap. It shifts left the visibility and intelligence implementation teams have always had, putting them directly in the hands of front-end designers at the moment they're most useful.

The name change goes beyond appearance; it indicates that this tool supports the entire PPAC process—from initial RTL design to final production implementation.

Learn more about Cadence RTL Design Studio.

The product formerly known as Joules RTL Design Studio is now Cadence RTL Design Studio. No changes are being made to the product at this time.

The Truth About Complete DFT Flow: What Most Engineers Miss

2026-07-14T05:30:00Z

Design for Testability is a critical step in achieving high-quality silicon. In this Training Bytes blog, we are going to explore implementing an efficient DFT flow using the Genus Synthesis Solution, covering key concepts such as synthesis with test, scan insertion, test readiness, and preparing your design for ATPG with Modus and for fault diagnostics.

Synthesis with DFT
In this section, we introduce the DFT implementation flow using the Genus Synthesis Solution. These videos focus on preparing your design for test by integrating DFT architectures early in the flow.

Ever wonder how DFT fits seamlessly into your synthesis flow? Check out our short byte on YouTube titled: A Design with Test Circuit where you can explore your design with test structures.
Adding test structures in your design requires some Basic DFT Rule Checks. The intent of these checks to ensure the elements put in the scan chains are shifting data properly.
DFT isn’t just an added step, it is the backbone of test-ready design. To make the design test ready, you need to fix violations; for example, Fixing Asynchronous Set and Reset Pin Violations. You can also run the DFT rule checker and fix the DFT Violations on a Scan-Mapped Design at any stage in the synthesis with DFT Flow.
To increase the coverage of your design, Insert Test Points Manually during synthesis.
You can also Insert Shadow Logic Around the Untestable Logic to increase the design’s controllability and observability.
To access the functional ports of your chip independent of system logic, Insert the Boundary Scan Architecture in your design.
You can also learn to add other test structures, such as Memory Built-In-Self-Test (MBIST) and Logic Built-In-Self-Test (LBIST). See our YouTube videos: What is MBIST and What is Logic BIST.

ATPG Flow with Modus DFT Software
Once your design is synthesized and includes the test architecture, you can seamlessly handoff to the Cadence Modus DFT Software solution to run the Automatic Test Pattern Generation ATPG flow. See the following steps and embedded links to the respective topics:

To understand Modus ATPG Flow Steps and its Graphical User Interface, watch the embedded video.
The first step is creating a Modus model, defined by Build Model. It does this by reading the design netlist and reading the structural library files combining together to create a design image. This model will be used for all further steps in the ATPG flow.
You can also build the test mode to set up the device for testing, as described in: What Is Test Mode.
To update the global fault list faults detected in the design, watch the video: What Is the Commit Experiment?
If you are curious about writing the industry standard test vector, click on the embedded link and watch the video ATPG Vector Generation and Writing the Patterns.
You can also debug the broken scan chains in your design by Debugging Broken Scan Chains using the Modus GUI or How to Debug Broken Scan Chains using Tcl Interface in Modus DFT?

Diagnostics with Modus DFT Software
Once your test patterns are generated, the real challenge begins—diagnosing manufacturing defects and identifying faults. Modus Diagnostics assists in identifying the root causes of defects in manufactured digital semiconductor devices.

Identifying the root cause facilitates corrective actions to avoid future defects and improve product yields. The Modus Test Diagnostics Overview is a good resource to start with.
Because there is no industry standard, failures from Automated Test Equipment (ATE) are reported in a variety of ASCII formats. You can convert your Tester Fail Data to Chip Pad Pattern CPP Format.
Modus has established a simple input Failure Format Called Chip Pad Pattern (CPP) file.
Once you Read the Tester Failure Data into binary format, you start diagnosing the failures in your design.
With Modus diagnostics capabilities, you can Diagnose Single/Multiple Manufacturing Defects in the functional logic of the chip, select all the faults in the logic back cone of the flops, then perform fault simulation and compare the results.
Modus DFT Software provides a wrapper that allows you to execute all steps, including determining if the failures are on Logic or Scan patterns, in one command. You can get more information by watching this Demo.

For more such videos and training bytes, login to Cadence Learning and Support Portal.

For technical shorts, subscribe to Cadence's official YouTube Channel

Boost Design Productivity by Cadence Digital Tools: Webinar Recording Available!

2026-07-02T03:30:00Z

This webinar series delivers practical methodologies and tool insights to help digital designers keep pace with growing complexity and meet aggressive tape out schedules with confidence. (read more)

Mastering Advanced Debug in Conformal LEC: Mapping to AI Driven Abort Resolution

2026-07-01T04:53:00Z

This blogs provides a structured learning approach to Conformal LEC debug that combines mapping, systematic NEQ and abort analysis, and AI-driven automation to accelerate equivalence closure.(read more)

Smarter DFT Starts at RTL: A Deep Dive into Modern DFT Flows with Genus

2026-06-30T18:00:00Z

This blog showcases the benefits of integrating DFT features within the synthesis task to deliver early and physically aware test flows for better PPA, cleaner scan architectures, and faster convergence.(read more)

Digital Design

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Setting Sail: Bringing the Design into the Physical World

Charting the Map: Defining the Territory

Navigating Complex Landscapes

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Automating the Wisdom of Experience

Powering the Voyage

Reaching Ithaca: Completing the Floorplan

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Might of Design Exploration: Deep Dive of Exploration Techniques in Stratus HLS

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