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In recent years, power consumption has moved to the forefront of digital IC development concerns. Design teams across the semiconductor industry are adopting efficient power management techniques to address the new power-related requirements such as improved battery life, reduced system cost, cooler operation, and improved reliability. Thus, in order to meet aggressive design schedules of enormously complex SOC designs, it is wiser not to consider power only in the implementation phase but throughout the development process.
Now the question arises, how do you implement a design flow that holistically addresses the architecture, design, verification, implementation, and signoff of low-power designs?
The Cadence Low-Power Solution is here to help you. This design flow considers power at every step of the design flow, from the chip/system architectural phase through design (including micro-architecture decisions) all the way to implementation with power-aware synthesis, placement, and routing. It does make trade-offs and optimizations for leakage and dynamic power to deliver a low-power design with high Quality of Results (QoR). It supports both the IEEE 1801 and CPF industry-standard formats for power intent and helps verify that the low-power design is compliant with the specified power intent.
This Low-Power Solution signals you that the decisions you make earlier on, such as your algorithms and IP, as well as architectural decisions such as multi-voltage islands, and power shutoff or sleep modes, will have a bigger impact on your power as compared to decisions you make at synthesis, place-and-route, and production. This diagram illustrates that the earlier on you make those types of decisions, the more power you can save.
Apart from the design implementation and optimization, to prevent functional issues from surfacing in the final silicon, power-aware verification must be performed throughout the development process. In the case of low-power designs, Cadence Conformal Low Power Solution combines equivalence checking and implementation checking of the low-power logic, using formal techniques to enable full-chip verification of designs optimized for low power.
In summary, the design, implementation, and verification tools and flows provided by Cadence address all areas of power management and are design-proven to solve the SoC low-power problem comprehensively.
To assist you in further learning, we have some short videos and articles on Low Power Design and optimization available on our Customer Support site.
Understanding terminology and basics of Low-Power Design (cadence.com)
Understanding the Type of Cells used in Low Power Designs (Video) (cadence.com)
Low Power Optimization Using Always-on Buffers (Video) (cadence.com)
Online Training and Resources
If you find the post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design:
Low-Power Flow with Innovus Implementation System v21.1 (Online)
If you are embarking on your learning journey with Cadence, here are some tips and resources to get you started:
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