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Low-Power Implementation Training Videos
By
VNelson
|
21 Apr 2021
Hello Digital Designers, Interested in learning more about how to implement a low-power design? Do you have multiple voltage islands that need level-shifting, and isolation, and also require a CPF or !EEE 1801 power intent definition file? Do you need to reduce leakage and dynamic power? We have just released several training videos that can answer many of your low-power questions. The newly released videos...
0 Comments
Tags:
Low Power
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Digital Implementation
|
Innovus
|
Power Analysis
Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protection
By
Priya E Joseph
|
21 Apr 2021
This blog discusses the different Voltus electrostatic discharge (ESD) checks in the form of rules to ensure your design is protected against ESD.
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Tags:
effective resistance
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Silicon Signoff and Verification
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electromigration
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Voltus IC Power Integrity Solution
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Power Signoff
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electrostatic discharge
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current density
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Power Integrity
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Full-Chip
|
ESD
Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier with Conformal Equivalence Checker
By
Atreya
|
14 Apr 2021
You put your design through a multitude of tools for various transformations. Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but wait... there is an easier way: Use equivalence checking, with Conformal® Equivalence Checker. And that easier way is made even easier with these videos on how to do your equivalence checking, along with a few of the...
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Tags:
conformal
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formal
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Logic Design
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Equivalence Checking
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Digital Implementation
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verification
Library Characterization Tidbits: Define Measurements to Suit Your Characterization Requirements
By
Jommy
|
30 Mar 2021
Do you have a requirement to specify measurements that are not default while performing memory characterization? Liberate MX has a solution for you.
0 Comments
Tags:
memory characterization
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define_measure
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Liberate MX
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Library Characterization Tidbit
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Liberate Characterization Portfolio
iSpatial: Next-Generation Common Physical Optimization Flow
By
Neha Joshi
|
22 Mar 2021
With advanced-process nodes, a standard cell's physical delay, net delay, and congestion all lead to a higher netlist requirement. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optim...
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Tags:
Genus
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Logic Design
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Synthesis
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ispatial
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physical implementation
Voltus Voice: Demystifying ESD — Four Simple Steps to Run ESD Analysis Full-Chip Flow
By
Vijetha
|
9 Mar 2021
This blog post outlines four simple steps for analysis of your electrostatic discharge (ESD) protection circuitry using the Voltus ESD Analysis solution.
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Tags:
effective resistance
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Silicon Signoff and Verification
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Power Signoff
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electrostatic discharge
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current density
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Power Integrity
|
Voltus
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Full-Chip
|
ESD
Library Characterization Tidbits: Importance of Noise Analysis and the Role that Liberate Plays
By
Moinak Gorai
|
4 Mar 2021
The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe defined as any kind of unwanted signal that interferes with the real signal in a timing path in a cell or circuit. Modeling of accurate noise characteristics at the cell level and being aware of the possible failures early...
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Tags:
CCSN characterization
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CCSN
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Liberty Variation Format
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Reference-based modeling
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cross coupled capacitance
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characterization
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composite current source noise
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noise in digital circuit
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CCS Noise
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Library Characterization Tidbit
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channel connected blocks
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coupling cap
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Liberate
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noise propagation
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Liberate Characterization Portfolio
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Stage-based modeling
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CCB
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timing
Understanding Clock Gating Report and Cells
By
MJ Cad
|
19 Feb 2021
Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive clocked elements to have gating logic automatical...
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Tags:
digital badge
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blended training
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Genus
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training bytes
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Digital Implementation
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online training
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cadence learning and support
Voltus Voice: Power-Saving Chip Design Is Not a Choice; It’s a Necessity
By
Ramesh Sharma
|
9 Feb 2021
A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.
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Tags:
Low Power
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Silicon Signoff and Verification
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static power
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Voltus IC Power Integrity Solution
|
low-power technique
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power gating
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Power Integrity
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rush current analysis
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Innovus
Library Characterization Tidbits: Recovering from Failures in the Multi-PVT Characterization Flow
By
Rajni
|
5 Feb 2021
Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the recovery workflow in the multi-PVT characterization flow! Read more...
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Tags:
Liberate Trio Characterization
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Multi-PVT
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Recharacterize
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library characterization
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Library Characterization Tidbit
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Digital Implementation
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PVT corners
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failed arcs
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Liberate Characterization Portfolio
|
recovery flow
All You Need to Know about Application Engineering in EDA
By
Pankaj Khandelwal
|
4 Jan 2021
"How many tape-outs have you done?" asked the design manager of a semiconductor company. My colleague and I were on a call with him to walk him through an implementation training agenda. He further explained the intent of the question “I am looking for trainer who has hands-on experience in implementing design. I want the training to be more design challenge oriented rather than just talking about command and switches...
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Tags:
application engineering
|
AE
Voltus Voice: Power Integrity and Signoff in 2020 – A Jog Down Memory Lane
By
Priya E Joseph
|
30 Dec 2020
Voltus TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy...
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Tags:
Silicon Signoff and Verification
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electromigration
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Voltus IC Power Integrity Solution
|
Power Integrity
|
IR drop
Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and Alleviate Wiring Congestion in the Clock Path?
By
MJ Cad
|
17 Dec 2020
Hi everyone, Searching for yet another method to improve the QoR of your design? What about taking advantage of the improvements in area and power that the Multibit Cell Inferencing (MBCI) flow provides? Merging to multibit cells refers to the merging of the individual register bits from the same or different bus into multibit cell instances. That way, a single clock pin can be used to trigger all register bits in...
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Tags:
blended training
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Genus
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training bytes
|
Digital Implementation
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online training
|
Cadence support
Library Characterization Tidbits: Bidding Adieu to 2020
By
Jommy
|
17 Dec 2020
This year all our “regular” routines were shaken up by COVID-19, which brought along many challenges for people all over the world.
0 Comments
Tags:
library characterization
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Library Characterization Tidbit
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Digital Implementation
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Liberate Characterization Portfolio
Wondering What to Do During the Winter Staycation? How about Learning Something New?
By
VNelson
|
15 Dec 2020
We just recently released a training course that we are excited to tell you about. The course is RTL-to-GDSII Flow . This course is unique in that it takes a tiny design through a wide variety of Cadence tools so that you can gain some exposure to tools that you may not be familiar with. You learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by learning how to code a design in...
0 Comments
Tags:
conformal
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Genus
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Tempus
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modus
|
Voltus
|
Digital Implementation
|
Innovus
Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the Rescue
By
sakshin
|
14 Dec 2020
This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow.
0 Comments
Tags:
Silicon Signoff and Verification
|
electromigration
|
Voltus IC Power Integrity Solution
|
electrical-thermal
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Digital Implementation
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FinFET
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self-heating effects
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IR drop
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Full-Chip
Innovus Design Metrics: Visualize This!
By
VNelson
|
2 Dec 2020
To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options. You will then need to analyze the data which could mean wading through several log files and timing reports, a time-consuming task at best. To make it easier to visualize the data by generating an easy-to-read dashboard, Innovus now has integrated metrics commands...
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Tags:
Innovus
Library Characterization Tidbits: Rewind and Replay - 3
By
Jommy
|
19 Nov 2020
This blog provides a summary of the last five blogs posted in the Library Characterization Tidbits blog series.
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Tags:
constraint probes
|
minimum period arc
|
Liberate LV
|
encounter
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library characterization
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Liberate MX
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Library Characterization Tidbit
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Digital Implementation
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Liberate Characterization Portfolio
|
library validation
Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve Big-Data Challenges
By
timjedwards
|
10 Nov 2020
This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks among thousands of CPUs while seamlessly processing terabytes of data.
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Tags:
Silicon Signoff and Verification
|
Voltus IC Power Integrity Solution
|
Multi-Physics Technology
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Power Integrity
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cloud
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parallel processing
|
distributed processing
Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 2
By
AbhaRawat
|
5 Nov 2020
This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.
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Tags:
Liberate Trio Characterization
|
tidbits
|
Liberate AMS
|
Liberate LV
|
Liberate Variety
|
library characterization
|
Liberate MX
|
Library Characterization Tidbit
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Digital Implementation
|
Characterization Solution
|
Liberate
|
Liberate Characterization Portfolio
Voltus Voice: Accelerate Power Signoff and Design Closure with Targeted Local PG Addition
By
AndreaBarletta
|
20 Oct 2020
This blog is in continuation with the post on the IR-Aware placement technology that is used at the early design stage to mitigate IR drop hotspots and ease final signoff. The second part of this blog discusses targeted PG stripes addition, another IR drop-centric technology to localize and remove the remaining hotspots.
0 Comments
Tags:
Innovus Power Integrity
|
Early Rail Analysis
|
Silicon Signoff and Verification
|
rail analysis
|
Voltus IC Power Integrity Solution
|
Power Integrity
|
Digital Implementation
|
Innovus
|
Power Analysis
|
IR-Aware Placement
|
Placement
|
design closure
|
IR drop
Library Characterization Tidbits: Characterize Minimum Period for Memory Instance Using Liberate MX
By
HelenShi
|
9 Oct 2020
In this blog, I will talk about the minimum period arc, which is a critical arc associated with the clock of a memory instance.
0 Comments
Tags:
memory characterization
|
self-timed memory
|
clocking scheme
|
minimum period arc
|
library characterization
|
Liberate MX
|
Library Characterization Tidbit
|
Digital Implementation
|
externally timed memory
What’s inside Joules Graphical User Interface!!
By
Neha Joshi
|
28 Sep 2020
Power is HOT and it touches everything and everybody! But we can help with power analysis for your chip!! Do you want to: Sneak peek inside the schematic? Analyze power for various blocks? Identify the relation of hot cells with RTL? Explore annotation settings? Joules RTL Power Solution GUI (Graphical User Interface) helps you to analyze/debug the power estimation/results using several GUI capabilities...
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Tags:
gui
|
Joules
|
Power Analysis
A Refresher on the Basics of Timing Analysis and Signoff
By
Atreya
|
21 Sep 2020
Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing Signoff in Digital Implementation. The smaller nodes - le...
0 Comments
Tags:
Static timing analysis
|
Digital Implementation forums
|
Tempus
|
Signoff Analysis
|
STA
|
training
|
Digital Implementation
Voltus Voice: Accelerate Power Signoff and Design Closure with this IR Aware Placement Technology
By
AndreaBarletta
|
21 Sep 2020
This blog introduces the Innovus Power Integrity Solution that integrates the Innovus Implementation System and Voltus IC Power Integrity Solution to alleviate signoff bottlenecks and provide faster convergence at the end of the flow.
0 Comments
Tags:
Innovus Power Integrity
|
Early Rail Analysis
|
Silicon Signoff and Verification
|
rail analysis
|
Voltus IC Power Integrity Solution
|
Power Integrity
|
Digital Implementation
|
Innovus
|
Power Analysis
|
IR-Aware Placement
|
Placement
|
design closure
|
IR drop
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