The Fuller View Blogs

SAN FRANCISCO—Third-party IP integration is crucial not only to managing system-on-chip (SoC) design complexity but getting to market in a reasonable amount of time. But this is often easier said than done. If done improperly, design teams can experience schedule slips, which means added cost and lost market opportunity. So is third-party IP integration worth the risk? Are there any real alternatives? These were fundamental...

SAN FRANCISCO—On the long winding road to the Internet of Things, are we there yet? That was the very question addressed by a panel at the 52nd Design Automation Conference here (June 11): “The Long and Winding Road to IoT Connectivity: Are We There Yet?” Panelists, led by moderator Nick Sargologos, marketing manager with Freescale’s Digital Networking Division, agreed that it’s probably best to think of it as a journey...

SAN FRANCISCO—A team from Cadence’s IP Group walked away from the 52 nd Design Automation Conference with a big feather in its cap: A best-paper presentation award. DAC IP Track Chairman Mac McNamara, now CEO at Adapt IP , announced the award just before the closing keynote presentation. The Cadence team was honored for best presentation at the IP track for its paper “Design in the Eye of the Hurricane—Building...

SAN FRANCISCO—Can engineers use what Silicon Valley hath wrought to create a virtual Silicon Valley for the rest of the world? That was the intriguing question before panelists Wednesday, June 10 here at the 52 nd Design Automation Conference. Moderator Lucio Lanza of LanzaTech Ventures and winner of the 2014 Phil Kaufman Award took the concept of the Internet of Things and raised the question of whether the...

SAN FRANCISCO--Cadence IP Group CTO Chris Rowen has been talking up vision processing for some time now, and he came to the 52nd Design Automation Conference to offer some additional perspective. In a presentation as part of the conference's IP track, Rowen said balancing the need for compute power in vision applications and keeping power under control are key system-design challenges today. "Vision has clearly...

When you have the best R&D team in the business and a vision to transform synthesis as we know it, well, great things can happen. And this week Cadence had a little birth announcement designed to shake up the status quo: https://youtu.be/SvF-aMKRec8 To check out the technical details and supporting materials of the new Genus Synthesis Solution, check out the technology's home page . (And pass the video around!...

What are the biggest electronics systems design challenges of our time? Try mixed-signal implementation and verification. Try chip and system verification in general in an era when software is an increasingly important consideration. Try navigating the transition from established process nodes like 28nm to leading-edge nodes like 16FF+. Cadence engineers and partner experts fan out next week at the 52 nd Design Automation...

SANTA CLARA, Calif.—Jeff Bier has some good news and less-good news when it comes to embedded vision applications. “The good news is there is an enormous and growing diversity of processor choices for vision and that helps increase the odds of finding something that fits with your application,” Bier, the founder of the Embedded Vision Alliance , said recently. “The bad news is, there are lots of diverse choices and...

This is the story of how three rival Ph.D. engineers joined forces to start a company to attempt to disrupt power-management design in mobile devices. The moral of the story (spoiler alert) is, you can create a semiconductor startup in Silicon Valley these days with no experience; it just doesn’t look or feel like the ones in the TV show “Silicon Valley.” Harvard graduate and co-founder Wonyoung Kim came to Cadence...

SANTA CLARA, Calif.—The three keys to successful product development are: keep it simple, take time, and test, test, test. That was my take-away from Mike Aldred’s keynote address Tuesday (May 12) here at the Embedded Vision Summit . Aldred, electronics lead for Dyson, delivered a master class in product-development processes for a rapt audience of at least 500. Exhibit A was the Dyson 360 Eye robotic vacuum cleaner...

When it comes to pushing power as low as it can go, the answer is part technological, part cultural. That was the conclusion of a panel of experts at the annual Electronic Design Processes Symposium in Monterey April 24. The panel, moderated by Cadence blogger Richard Goering ( pictured far left ), was titled, “Can Power Go Any Lower, Or Have We Amost Hit the Floor, Especially for IoT Devices?” And experts from...

Ken Willis, product engineering director for high-speed signal analysis products at Cadence, has sweated his way through three episodes of So You Think You’re an Expert, our new series testing domain expertise. So far he’s nailed questions on the importance of minding the impedance tolerance of the traces in serial ink routing, on whether series termination is the best technique for daisy chain routing topologies...

In the first two episodes of our new series "So You Think You're an Expert," Cadence's Ken Willis tackled tough questions on impedance control and serial link routing. As he continues his march to become a domain expert in high-speed board design, Ken is confronted in episode 3 with even tougher questions. They're so tough that he needs to reach out to his lifeline, Dave Palumbo, aka the "Wizard," for help. How will...

True or false: The most important thing to control in serial link routing is the impedance tolerance of the traces. Will tighter impedance control of traces typically be achieved on external or internal PCB routing layers? What do you think? These are the types of questions we’re putting to Cadence experts as part of a new series “So You Think You’re an Expert,” designed to elevate training programs in various Cadence...

SAN JOSE, Calif.—Trumpeting an industry that “can move the world,” the President and Co-CEO of TSMC unveiled a new low-power process for Internet of Things designs, described expanded R&D process investment, and highlighted the quickening pace of technology introduction in a keynote at the annual TSMC Technology Symposium. Dr. Mark Liu ( pictured, right ), addressing an immense convention center room here packed with...

It’s a defining moment in electronics design history: The ecosystem now stands astride two major paths. The first is the traditional, relentless drive toward the next advanced node for leading-edge designs. The second path pushes teams toward optimizing mature nodes. This has taken on new meaning because of the value these mature processes bring toward Internet of Things (IoT) designs. On the eve of the annual TSMC Technology...

The just-announced Innovus Implementation System aims—among other things—to call a truce in the long design tradeoff tug-of-war between optimizing power, performance, and area (PPA) and maintaining or improving turnaround time (TAT). Indeed the Innovus system, announced March 10 at CDNLive , aims to help design teams optimize both PPA and TAT and improve both in the process. Anirudh Devgan described the technology...

NUREMBERG, Germany—System design complexity requires new solutions not only to conquer that complexity but keep the pace of design robust. No longer do engineering teams toss hardware or software over the wall and wipe their hands. Software must be considered early in the design flow but solutions here vary. “SoC developers want to use software to verify system-level use cases and reuse these tests in simulation...

SANTA CLARA, Calif.—Cadence’s new Innovus Implementation System ushers in “a new era” in physical implementation technology and engineering productivity, enabling faster turnaround times, better power, performance, and area (PPA) optimization, and capacity to handle bigger design blocks. That was the word from Rahul Deokar, product management director with Cadence, who gave a technical overview of the new technology...

Srdjan Djordjevic, senior sales technical leader at Cadence, has been a busy man carrying the banner for automotive design solutions. Earlier this year he attended an automotive congress in Munich where he showed an ECU-ECU simulation demonstration using Allegro Sigrity tools. He said: “You have extraction of the first electronic control unit PCB using a finite solver or 3D element extraction solver. Then we had assembly...

SANTA CLARA, Calif.— Given the continuing constraints in the battery-life improvement and pressures to add new features and functions, engineers must change the way they design electronics systems to keep pace with future demands, the CEO of ARM Ltd. said. Simon Segars brought his company’s message of design efficiency and power optimization to his keynote address at CDNLive Silicon Valley 2015, saying, “Battery technology...

SANTA CLARA, Calif.—Increasing technology complexity, time-to-market pressures, and the quickening pace of innovation are forcing a “sea change” in electronics system design that can only be navigated by thinking differently about systems. That was the message from Cadence CEO Lip-Bu Tan, who kicked off the company’s annual CDNLive Silicon Valley event here with an overview of industry challenges and opportunities...

Technical press coverage traditionally focuses on the bleeding-edge nodes because that’s where the biggest challenges are. But today, our industry sits astride two distinct paths: One, next-generation process nodes. But the second path is mature nodes, which are getting extended life thanks to exploding markets such as the Internet of Things. And those mature nodes—and attendant methodologies — are constantly being...

BARCELONA, Spain—Much of the promise of coming innovation in big applications spaces—industrial control, automotive and the Internet of Things—rides on video. But video is demanding in its needs. For it to be effective, it needs support of robust processing. For it to be cost effective, it needs certain area constraints. For it to be attentive to system design needs, it needs to be power sensitive. Much of these...

NUREMBERG, Germany—Timed with Embedded World 2015, Cadence announced its new Stratus High-Level Synthesis Platform, a combination of the “best of both” Forte’s Cynthesizer (acquired in 2014) and the Cadence C-to-Silicon Compiler HLS tool (Richard Goering elaborates on the announcement here ). Frank Schirrmeister, Cadence group director for the System Development Suite, traveled to his native country to brief the European...