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SAN JOSE, Calf.--Pop quiz: What percentage of
verification time do design teams spend on re-iterating their layout design
after checking electrical parameters?
If you said 30-40 percent, move to the head of
And given the ceaseless increase in design
complexity, you'd expect that percentage to balloon as we move deeper into
ultra-deep submicron geometries. But a new methodology addressing
layout-dependent effects has emerged to address the challenge and improve
Electrically aware design (EAD) enables design
teams to do electrical verification incrementally in real time as each physical
layout design decision is made. It fundamentally moves verification earlier in
the design flow.
Cadence's David White (pictured, left), Group Director for
Virtuoso EAD, laid out the new frontier during a recent presentation at ICCAD here.
"As we introduce these
new silicon technologies, we're seeing difficulty in trying to maintain design
intent through layout and into verification. At the same time, there's a need
for more in-design verification methods to catch problems during design. The
tools need to be faster and use unified common data models."
In the conventional flow, White said:
"A series of decisions
are made with regards to placement and routing and not until you get to the end
doing LVS and DRC can you do parasitic extraction and re-simulation and you
might do something like EM checking for reliability."
Therefore, you can't know the electrical
consequences of all your layout decisions until that's done, and it's very
difficult to go back and make changes, White said.
The need at advanced nodes is acute, because of interconnect
and proximity issues which can enhance electromigration problems.
"No longer can you just check the
electromigration for a given shape," White told the audience. "You
have to look at the shapes around it."
You could, for example at earlier nodes, look at
three identical vias and conclude that they have the same EM limits. But at
advanced nodes, the wires going into and out of those vias can impact the via
EM characteristics and the rules you need to apply.
A connectivity-driven environment enables the
kind of in-design electrical feedback that teams need to tackle these advanced
node issues and improve productivity, White said.
"You need a way to
continually maintain connectivity to ensure the layout is in synch with the
schematic. The way to do that is you
create a connectivity-driven environment that can do this in real time."
The solution--the new flow (pictured, right)--needs to produce no noticeable lag,
match the level of abstraction used by the designer, and be accurate and fast.
Doing that with conventional verification tools
would require multiple tool invocations and many database translations. It also forces
multiple scripts to be managed.
With a shape-based data model, in-design analysis
can be done on a net-by-net basis, which is the way real layout is generated,
At extraction, using an incremental approach, each
change can be evaluated. The approach translates a geometric description of the
shapes to their electrical equivalent. The extracted parasitics become
available as each incremental change is made, White said.
You maintain speed by taking advantage of things
like machine learning to "basically mimic the answers you'd get from a
field solver," White said.
"You could use a field solver --
take the geometric descriptions of test patterns, run them through a field
solver and train the pattern-matching extractor to mimic the input and output behavior
of the field solver. You build up the
models, which go into a techfile and that gets loaded with the layout, and
that's one way you can create extraction methods that are fast and accurate."
As electrically aware design flows evolve, early
solutions will focus on parasitic and parameter extraction, White said.
Electrical analysis solutions will build on core extraction technologies and
initial analysis solutions will leverage fast resimulation and EM, he added.
"We believe in-design
solutions are the next major wave for
EDA, especially in the physical implementation piece and being able to tie
simulation much closer to layout creation and optimization... (In this way
designers can be) focusing on correct by construction rather than waiting until
the end ... and iterating back through."
Here are two resources that provide more information about electrically aware design as a methodology:
Electrically Aware Design (EAD) - A New Approach to Custom/Analog Layout