Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
FRANCISCO--Electronics system design teams need to discard old ways of
thinking, be creative, and work more collaboratively if the industry is to
deliver on the promises of advanced node technology, TSMC's R&D vice
conventional wisdom that led to our success in the past will no longer work in the
future," said Dr. Cliff Hou, during his keynote at the 51st Design Automation
of example, Hou (pictured) said:
"We need to work in
a concurrent way between EDA and processes. EDA cannot wait until a process is
ready to start development. Similarly, process rules can't be set without
considering all EDA requirements in the future."
outlined a vision for the evolution of advanced nodes from 20/16nm down to
below 10nm that emphasized partnership and innovation during his hour-long
presentation at the Moscone Center June 2.
20/16nm, for example, EDA vendors are working to solve the coloring issue
required because of double patterning lithography.
don't design your process node carefully, easily you can lose one fin," Hou
said. Losing one of four fins (25%) means a major design hit, he said. "You
have to make sure all the design steps are using coloring; otherwise, the whole
flow is broken," he added.
In a presentation
earlier this year at the TSMC
Technology Symposium, Hou described the company's two current 16nm offerings --
16nm FinFET (16FF) and 16nm FinFET Plus (16FF+). The "plus" line is a
second-generation FinFET technology that provides power, performance, and area
looked ahead to 10nm and beyond, he looked back briefly, saying, "We've done a pretty good job in the
last decade." At 10nm and below, "I think from a process point of view, we
can provide PPA (power, performance and area) improvements but development
costs will be high. We have to find the best solution. Every penny will count at 7 and 10nm."
earlier presentation, Hou said TSMC is actively working on 10nm. Early customer
engagements are underway, tapeouts are expected in 2015, and risk production is
planned for late 2015. The 7nm process node is heading for risk production by mid-2017, and
preliminary design rules for early test chips will be available in 3Q 2014.
else did Hou see in his DAC keynote technological
crystal ball? Lithography, Hou said, will
lean on immersion technology for as long as possible. TSMC is also
considering directed self-assembly as an option at 16nm half pitch.
FinFETs will probably be useful to the 7nm node. After that, Hou sees the industry
embracing nanowire or gate-all-around structures and perhaps III/V materials to
enable supply voltages of half a volt and below. Resistivity is becoming a bigger issue for interconnect at 16 and 10nm, thanks
to narrow wires. Design engineers may have to
consider different metal pitches to resolve the situation, he added.
closed by saying:
"With the new
challenge at 10nm and beyond, it creates new opportunity for new innovation and
new ways of thinking. Whoever has the new idea will win. To keep PPA scaling at
10nm and beyond requires tighter collaboration between process nodes, design,
EDA, and IP. The message here is conventional wisdom no longer holds. We need to
have a different mindset, a different working model for 10nm and beyond."
-- DAC 2014:
Mixed-Signal Designers Cite Verification Challenges, Solutions
-- DAC 2014:
Computer Vision Coming but Requires Engineering Flexibility, Creativity
-- DAC 2014
Keynote: Qualcomm VP Outlines Mobile Computing Challenges