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October 7, 2014--The ARM Cortex-M7 processor is out, developed to address digital signal control markets that demand a blend of control and signal processing capabilities. The ARM Cortex-M7 has been designed with a wide variety of highly efficient signal-processing features to address the design demands of market applications such as next-generation vehicles, connected devices, and smart homes and factories.

In many of these end markets, engineering teams demand:     

  • Maximum performance within power budgets   
  • Maximum power savings targeting a given frequency

These are significant challenges to address, so how do we deal with them?

(Cadence recently published a white paper that details the challenges and some solutions. It described ways in which Cadence and ARM worked to optimize power and timing closure in the ARM Cortex-M7.)

We start by identifying and confronting the issues. Let’s take dynamic power, for example. Dynamic power is the largest component of total chip power consumption (the other components are short-circuit power and leakage power). It can quickly become a design challenge in leading designs.         

Then there are timing-closure challenges. One fundamental timing closure issue is the modeling of physical overcrowding. Among other things, this problem can be addressed by deftly managing layout issues (such as placement congestion, overlapping of arbitrary-shaped components, and routing congestion).

K.T. Moore, Group Director in Cadence’s Digital and Signoff Group, said:

“Closure requires a different way of thinking. You have to consider multiple constraints in the closure process with a unified objective function in mind. This is easier said than done because many constraints conflict with each other if you simply address their effects only on the surface.”            

In the past, teams relied solely on post-route optimization to salvage setup/hold timing in tough-to-close timing situations. But now we can rely on in-route optimization to bridge timing closure earlier during the routing step itself using track assignment.

In addition, opportunities exist to reduce area and gate capacitance in other ways.

The Approaches     

Among several methods, the team explored placement optimization using the GigaPlace engine, available in Cadence Encounter® Digital Implementation System 14.1. GigaPlace places the cells in a timing-driven mode by building up the slack profile of the paths and performing the placement adjustments based on these timing slacks.

The team also trained its sights on using in-route optimization for timing optimization to help hit the final frequency target.

Lastly, the team introduced the “dynamic power optimization engine” along with the “area reclaim” feature in the post-route stage. These options saved time and cut by nearly half the gap that earlier existed between the actual and desired power target.

By the end of this exercise, the team achieved power savings greater than 35% on the logic (excluding constants like such as macros and so forth).

For complete details, check out the detailed white paper here.


Brian Fuller

Related stories:

-- ARM Rolls Cortex-M7 Processor for Performance, Power Optimization

-- Whitepaper: Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design