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SANTA CLARA, Calif.—Cadence’s new Innovus Implementation System ushers in “a new era” in physical implementation technology and engineering productivity, enabling faster turnaround times, better power, performance, and area (PPA) optimization, and capacity to handle bigger design blocks.
That was the word from Rahul Deokar, product management director with Cadence, who gave a technical overview of the new technology at CDNLive Silicon Valley on March 10, 2015.
Innovus “enables a new era. Older implementation tools had forced you guys as designers to do smaller design blocks,” he told a standing room-only audience at the Santa Clara Convention Center. “You can now handle 5-10M instance design blocks…and you can take weeks or even months off your SoC design schedules.”
The new technology represents a fundamental overhaul of the Encounter system that “leapfrogs” the industry and delivers a far more compelling digital implementation solution than the industry has experienced, Deokar said.
Previously, optimizing for PPA and improving turnaround time was an either-or choice, he said.
"These were two conflicting objectives in a lot of ways. Traditional tools have effectively tackled just one or the other, however what good is it if the tool runs super-fast but ends up with sub-optimal PPA,” Deokar (pictured, right) said. “Innovus gets you the best of both worlds on turnaround time and PPA.”
By delivering performance that is up to10X faster, design blocks that took 7-10 days can now be run in 1-2 days, and the 10-20 percent PPA improvement is equivalent to a half-node or even a full-node transition, without actually moving to the new node.
Furthermore, because the technology is integrated with Cadence signoff solutions, significant additional productivity gains can be achieved as well along the flow, he added.
And Innovus is not targeted at just bleeding-edge nodes such as 16/14/10nm; it has vast utility for established process nodes as well, Deokar said.
A massively parallel architecture is key to improved turnaround time, Deokar said. The core algorithms have been improved such that “even if you're not running on 16 or 32 or 64 CPUs, the core algorithms of placement, optimization, and routing have been sped up. Even on 2- and 4-CPU machines, you should be able to see turnaround-time advantages,” he said. “Now, add multithreading, distributed network processing, and MMMC (multi-mode/multi-corner) scenario acceleration, and you get the complete massively parallel system.”
That means really large chips that forced teams to divide the SoC into many blocks to manage the placement and routing complexities can now work with fewer blocks, which cuts design time and saves money, Deokar said.
He cited as one example a 28nm 2.8 million-cell networking IP running on 8 CPUs (pictured) that saw implementation time cut from 336 hours to 48 hours—a 7X improvement.
The other key Innovus benefit for PPA represents a big step forward, he said.
Traditionally, placement ran on heuristic-based algorithms, but GigaPlace in Innovus is solver or equation based.
“That means you can model in the equation a lot of different design variables—timing, slack, power, wire length, congestion, layer awareness,” Deokar said. “GigaPlace concurrently solves both the electrical and physical objectives. As a result ,you get better PPA.”
Another feature is that Innovus is now power aware throughout the optimization process, Deokar said.
“All the transforms that were timing and area aware, now power is a part of that same cost function,” he told his audience.
A third key component is that the concurrent clock and datapath optimization technology from Azuro, which Cadence acquired in 2011, is now fully integrated.
“A lot of high-performance designers have unique clocking methodologies—H-trees, clock meshes, multipoint CTS,” he said. “You guys invest a lot of manual effort building these, but since these are customized, they’re not flexible when process and technology changes occur.”
The CCOopt FlexH feature integrated into Innovus is a combination of regular clock tree and H-tree, he said, “You get the best of both worlds in automation and in cross-corner variation, as well as in a high-performance and power-efficient clock network.”
Deokar also highlighted the track-aware optimization features of NanoRoute.
“Before you go into your detailed route step, right after track assignment to the different metals layers, we do timing-aware optimization,” Deokar said. “This proactively prevents signal integrity issues from occurring downstream in the flow, and dramatically reduces the timing jump between pre-route and post-route optimization.”
Finally Deokar noted productivity gains from the integration of Innovus with existing Cadence signoff technologies such as Tempus, Voltus, and Quantus, a common user interface and reporting and visualization enhancements.
More information about Innovus can be found by navigating to the technology's landing page.
- Anirudh Devgan at CDNLive 2015—How Innovus Will Change IC Implementation
- Anirudh Devgan Q&A: What’s Lacking and What’s Needed in Digital IC Implementation