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What are the biggest electronics systems design challenges of our time? Try mixed-signal implementation and verification. Try chip and system verification in general in an era when software is an increasingly important consideration. Try navigating the transition from established process nodes like 28nm to leading-edge nodes like 16FF+.
Cadence engineers and partner experts fan out next week at the 52nd Design Automation Conference to offer insights and guidance on these and other topics in a series of breakfasts and luncheons at the San Francisco Moscone Center.
I’ll be on hand to moderate, and I and Richard Goering will take turns writing up various panels to summarize what happened.
If you’re attending DAC, please consider carving out some time to join us for food and lively, insightful panel sessions. All will be held in Moscone Room 104 at the foot of the stairs at the entrance to the Exhibit Hall B/C. Here’s a rundown of our lineup:
Lunch on Monday, June 8 (Noon-1:30pm): How to Make Next-Generation Verification Smarter
Verification is at a crossroads again. Experts seem to agree that traditional, block-oriented dynamic verification techniques no longer scale to the next level of challenges. What’s next from here? Here venture capitalist and EDA legend Jim Hogan, Sanjay Gupta (Qualcomm), Alex Starr (AMD), Adnan Hamid (Breker), and Ziv Binyamini (Cadence) offer their insights to the challenges now and in the future.
Breakfast on Tuesday June 9 (7:30-9:00am): Crossing the Great Divide: How to Safely Navigate the Move from 28nm to 16FF+
When do you make the decision to move from 28nm? What are the biggest challenges at 16nm? How does the use of FinFETs change the design flow? These are among the most pressing questions in electronic system design today. Here experts such as Willy Chen (TSMC), Afshin Montaz (Broadcom), and Jayanta Lahiri (ARM) offer insights into the smartest ways to make the transition safely and effectively.
Lunch on Tuesday, June 9 (Noon-1:30pm): The Future of Digital is Here
If you’re designing SoCs for high-end applications—think cloud computing systems, mobility, networking, and the like—you can’t afford to sacrifice PPA or TAT. Your success depends on getting the best performing, lowest power chip to market before your competitors. Yet, the path toward this nirvana is bumpy at best, considering the new design challenges that emerge as process nodes shrink. Experts from companies including ARM (Raney Southerland), SoftMachines (Raj Khanna), and Cadence (Paul Cunningham) will offer a bird’s eye view of the design challenges from the teams on the front lines of innovation.
Lunch on Wednesday, June 10 (Noon-1:30pm): Methodology and Metrics for Analog/Mixed-Signal Verification: Madness or Marriage?
In this session, we might just have a little fun. Cadence’s Steven Lewis will play a “patient” stricken with anxiety over how to address analog and mixed-signal verification. Then we’ll invite experts from Maxim Integrated Products (Neyaz Khan), Semtech (Paul Margozzi), and NXP (Andre Gunther) to assess Lewis’ condition and prescribe treatment.
Check out the complete guide to Cadence’s 2015 DAC panels. Hope to see you there!
- DAC 2015: See the Latest in Semiconductor IP at “IP Talks!”