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were Cadence IP Group CTO Chris Rowen's words, as he presented (Sept. 17) a vision of the
future of electronics system design to a group of reporters, organized by Publitek, at the Alpine village of Tegernsee, near Munich.
most commonly, we talk about big data and deep insights in the context of the
Internet of Things (IoT). This is a spongy term that Rowen thinks will fade as
a buzzword soon.
fade because IoT is a broad umbrella for an almost innumerable number of widely
varying applications and devices. But to address these designs, it's useful to
think about the challenges in terms of what Rowen calls the "new data
imperative" and how that fits into "cognitive systems layering." And once we
understand that, how do we then enable those systems from conception all the
way through verification and system integration?
Rowen sketched the data imperative and cognitive layer hierarchy by using an example of how much energy it takes to move 64 bits of data, starting with the
lowest level (a 16nm FinFET NAND gate) and moving up to the cloud.
It is a linear plot from that lowest level, which consumes
nano watts of power and might awaken to detect noise and trigger a series of
system actions, up to 1W of power to access the cloud to perform full speech
recognition (see chart below).
"The lowest level is the only thing that's always on. When
you get to the cloud level, the system may be active only seconds per day.
‘Always on' systems means almost ‘always off.' That is the key to energy."
The data challenge that confronts the industry today is in its raw
explosion. As we corral more of the analog world into the digital back end via
sensors, the number of those sensors is soaring—an estimated 30 billion by
2017, according to Semico Research.
generating almost 1027 raw bytes of data. I looked it up to see
what's the little Latin phrase for that--exa, peta, zetta, yotta. There is not
yet a phrase for 1027, which gives you an idea of how dramatic this
amount of data is."
This data explosion is creating the need for engineers to consider new
approaches to system design that emphasize energy optimization and cognitive
that people are going to have to do cognitive layering...(that is) to have multiple levels of
processing typically related to multiple types of processors...to have only
enough processing of the right type being stimulated at any given level of
alertness of the system."
To implement this, it's helpful to have a holistic view of system
design enablement, a role Cadence plays from its IP/VIP offerings all through the
way through complete implementation and verification tools solutions and flows, he noted.
He noted that design
verification is growing because of the complexity of systems, the growing
number of possible modes of failure and potential vulnerability to malicious
are dealing more systematically with addressing low-energy requirements and
they're looking to (Cadence) to bring top-to-bottom know-how about
methodologies for low-power system design," Rowen said.
of that involves low-level device analysis, analog and digital integration,
library enhancement, and mechanisms for digital signoff, Rowen said, adding
some of it goes all the way up to algorithm optimization, multicore
architecture, instruction-set design, and software and system design analysis.
mission at Cadence is enable optimizations at all these levels because as you
go up this stack, you have an increasing degree of leverage on the energy
outcome," he said. "What you see in the Cadence flows is this
attention to this the energy analysis dimension."
Rowen cited as an example ways in which tools and IP such as the Tensilica Xtensa processor
can be combined "to do novel things."
The team took its baseline
Tensilica Xtensa processor (1.5GHz worst case in a 16nm FinFET process) and synthesized
and optimized it for low energy using the same RTL and then automatically
characterizing it "not at the standard cell but (using) SPICE directly on a
complete processor." He added:
"We can run real power and functional verification in about a
day on the SPICE model of one of these processors. We're getting down to 1
uW/MHz for this high-speed processor."
The system design approach is key when considering, as Rowen
says, that the design ecosystem's diversity is exploding and bifurcating into a
world of "mammals" and "insects." (Mammals have roughly 5,500 species, while
insects have millions). General-purpose electronics platforms such as cell
phones and servers are "mammals," while the IoT application space is composed of "insects." It's a space
where one size fits one size rather than all, and that requires a system design enablement mindset.
- CDNLive 2014: Follow the Data to Optimize System Design—Chris Rowen
- “Globalization of Processors” Transforming Electronics Design—Cadence’s Rowen