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SANTA CLARA, Calif.—When commercial formal verification tools started to take flight a couple of decades ago, a common quip was that the technology was “built by PhDs for PhDs.” That the technology had amazing promise was a given, but its ease of use and learning curves were challenges.
Those early days are long gone, but today formal verification technology faces new challenges, and conquering them will significantly change the face of verification and validation.
Ziyad Hanna, vice president for R&D and a Fellow at Cadence, boils it down to three major challenges—the need for:
“Formal is coming of age,” Hanna said during his keynote address to the 2014 Jasper User Group gathering here (Nov. 11, 2014). “But still it's not the main vehicle or technology for verification. You see the growth, but it's not there yet.”
Hanna, in a 45-minute presentation on the gathering’s second day, said formal techniques hold the promise of significantly altering the electronics design verification and validation landscape and driving widespread gains in productivity. But vendors and users need to work together to expand formal’s reach.
The technology’s democratization is evolving and it’s “very important to make formal available to all people.” Hanna, who joined Cadence from Jasper Design Automation in the spring of 2014 after Cadence acquired that company, suggested RTL designers in particular should be a target group for expanded use of the technology.
Hanna said designers are a good group to target because they sit at the top of the design funnel, focused on implementing a complex spec and having to cope with aggressive design implementation goals such as low power, timing, noise, and area. Thus, many logic bugs unintentionally slip to the RTL and then to the downstream netlist, Hanna said, adding that this causes very costly design iterations to correct the bugs.
Expanded use of formal verification methodologies up front with RTL designers can help eliminate some of these issues, he argued.
“There is a high cost of not doing this,” Hanna said. “If we push formal more with designers, we get high impact.”
Democratization needs to be a community effort, because the technology now resides in the hands of “experts.” Those experts need to collaborate and share their knowledge across design teams in their organization and work closely with vendors in the process.
Increased democratization will also happen as the tools get smarter and learn along with the users, he noted.
“The tool is smart enough to collect information and expose it to the user and be able to react to it. There's a loop happening here where the tool distills information and provides options to the users. The vision is about having the interface between the human being, the user, and the tool.”
Hanna said the other area of focus and growth for formal is scalability. Today's model checkers can be bounded by design size. Most can handle designs of 100 million gates, but eventual capacity should be 1 billion gates, he said. The other focus of scalability is in verification—the number of state variables that formal verification engines need to be able to handle.
Then there’s performance in the form of CPU runtime on formal. “Management can be very picky about cost. We need to reduce cost,” he said.
And, finally, technologists need to reduce the human debug effort using formal tools, Hanna said. With bounded model checking, Hanna said, “sometimes there's complexity we can't get by.” He said, however, that more elastic bounded model checking can overcome this, citing Jasper’s Leapfrog Bounded Model Checking product.
Lastly, Hanna touched on the importance—in the era of design methodologies platforms—of integrating formal more tightly into existing validation and verification flows.
“We are part of a bigger company and can leverage the technologies that we have,” Hanna said.
For IP design and integration, formal is key. But for system and SoC design, formal needs “to complement emulation and simulation” with approaches like formal-assisted emulation, formal-assisted simulation, and formal-assisted debug, he noted.
As an example, Hanna asked the audience to consider putting a device under test (DUT) through more analysis, optimization, dead code removal, and hierarchy smashing:
“A number of things could happen there leveraging formal technology that could happen to ... compact that DUT. Once that DUT is compacted, it can go into simulation and run much faster.“
Closing, Hanna said that from IP design all the way up through SoC and system design “I do believe that formal will continue to thrive and solve more and bigger problems.”
- JUG Keynote—How Jasper Formal Verification Technology Fits into the Cadence Flow
- Q&A: Kathryn Kranen Discusses Jasper, Formal Verification, and the Cadence Acquisition
- Why Cadence Bought Jasper—a New Era in Formal Analysis