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It’s a defining moment in electronics design history: The ecosystem now stands astride two major paths. The first is the traditional, relentless drive toward the next advanced node for leading-edge designs. The second path pushes teams toward optimizing mature nodes. This has taken on new meaning because of the value these mature processes bring toward Internet of Things (IoT) designs. On the eve of the annual TSMC Technology Symposium on April 7, I sat down with Suk Lee, Senior Director, Design Infrastructure Marketing Division of TSMC (pictured nearby), to get his sense for trends and challenges facing the electronics design ecosystem.
Q: Suk, talk a little about how TSMC views those different paths. And then how do you see the ecosystem at large preparing to navigate these two paths?
Lee: If you look at the history of the semiconductor industry, there's always been a large front-of-the-technology envelope engagement with customers and then there have always been trailing engagements. As you point out, we have strong design starts at two sets of paths now. We see this as an era of great opportunity.
People talk about the end of Moore’s Law, and it doesn't look like it's happening any time soon.The fact that we have bifurcated into two distinct paths means there is lots of demand for our silicon and vast opportunities for our ecosystem partners. We continue to field libraries and foundation IP for the leading edge, but frankly there's so much demand for our technology that we've increased the amount of development with IP partners in the ecosystem. That's spurred lots of opportunity for our IP and EDA partners.
Q: But this requires substantial continued investment, yes?
Lee: We expect capital expenditure in 2015 to be $11.5-$12 billion.That's a 25% year-over-year increase. Eighty percent of that is for advanced technologies. But we'll be adding 8-inch capacity; in fact, 20 percent of that capex we are investing in expanded 8-inch capacity. There was a rumor last year that we were backing off investing in older technologies, and that's clearly not happening.
We've had a wide portfolio spanning CMOS image sensors, MEMS, embedded flash, high-voltage processes, processes to support power-management ICs. We also have a broad portfolio in semiconductors, which is supported by packaging technologies, notably CoWos and InFO. You now have an opportunity to select the most mission-specific silicon and put it together on this high-performance packaging technology. With both CoWoS and InFO, not only is density super high but with the lower parasitics, the physics gives us a free ride for the first time in a long time. In other words, we get to have both better power consumption and higher performance by virtue of these technologies.
Toward the end of last year, we announced our ultra-low power platform. We've rolled out 55 ULP, 40 ULP, we've made the announcement about 28 ULP.
And, on 16nm, we expect more than 50 product tapeouts this year.
Q: Fifty? Five-zero?
Lee: Yes, five-zero. High-volume production will start in the third quarter, with meaningful revenue contribution starting in the fourth quarter of this year. You know the industry has always had the same fear since maybe 1 micron: How's the technology going to move forward? There aren't going to be any design starts, and then, boom, here we are.
Q: All that development you mentioned, that's a lot of work being done in parallel.
Lee: Well, we have 5,000 R&D engineers out of a total workforce of 43,000 people. That's a significant percentage. We devote 8% of our annual revenues to our next-generation technology development and that continues. We're going to keep pushing Moore's Law like crazy.
Q: You get feedback and insight from how customers are using your technologies. What can you tell us, in the context of this bifurcation, about how customers are using older nodes versus leveraging advanced nodes?
Lee: In terms of learning at the leading edge, the EDA industry talks of challenges, but the EDA industry has done a great job of supporting double patterning and our coloring technology, so that take-up of 16FF and 16FF+ has been very strong. On the older technologies, the major comment we can make is that given the new opportunities in IoT, low power consumption is a big focus for customers.
Q: Mark Liu (TSMC president and co-CEO) indicated at OIP last fall that 10nm is a fast-rising node, right behind 16nm. Where do we stand with 10nm development? Do you still expect customer tapeouts in the second half of 2015?
Lee: Our 10nm is progressing. We have completed certification of over 35 EDA tools using ARM's CPU core as the vehicle. In addition, we have started the IP validation process six months earlier than previous nodes with our IP partners. We are working with over 10 customers on their 10nm product design. The qualification schedule remains at the end of 2015. We are working with customers on tapeout, and we expect volume production in 2017.
Q: Can you share any insights on 7nm development?
Lee: I don't want to make any comment on a specific technology node number but we're working on future platform technology development. We have a team working on the next generation after 10nm. Those technologies are going to be offered in the 2017 to 2019 period. We don't anticipate Moore's Law is going to slow down anytime soon.
Q: Engineers apply lessons of any process node ramp to the subsequent process. What did 16nm learn from 20 and what is 10nm learning from 16?
Lee: The blogosphere about two years ago had some commentary about "wow 20 v. FinFET--that seems like a mistake." We had a conscious strategy, which was creating the ultimate planar technology with 20nm SoC and then spinning out 16nm FinFET with essentially the same metal stack. That was a great risk mitigation strategy for TSMC. We had a very advanced metal stack with a set of leading customers who wanted to squeeze every last drop out of planar. So 20nm turned into a great deal of business for us. We didn't have to take on two challenges at the same time—developing this complex metal system and bringing up FinFET. We've enjoyed the manufacturing learnings on the metal system, and that has made the ramp on 16FF much easier. You've seen in the press some of our competitors are struggling with their FinFET technology yields. Our technology has moved forward very smoothly.
Q: So how about from 16 to 10nm?
Lee: The thing that carries forward from 16 to 10nm is basic FinFET learning obviously, but also the techniques that we've refined on 16nm to handle multiple patterning segue smoothly into 10nm.
In general, one of the things we've done in the past four years is that we've engaged with the EDA/IP ecosystems earlier and earlier. We used to engage at SPICE 1.0. The pace of technology development and the pace of our customers' product cycles means that we've had to engage much earlier than in the past. For the ecosystem, one of the things that started at 28 and came to full fruition at 16 was that we mutually learned how to do process and full product all in parallel. That's really going to be a critical thing for 10. We're working with the ecosystem on 10. Our customers already are working on 10nm product designs. That's the result of the learning that we applied with the ecosystem on 28, 20, and 16 on how to do concurrent ecosystem and process bring up. That's enabled us to engage very quickly at 10nm.
Q: There’s been talk that the FinFET era will be a short one, perhaps only two or three nodes. Is that the case? If so, what’s next? If that’s not the case, how are we stretching out FinFET’s usefulness?
Lee: From 16 to 10nm to the next generation we’ve still got a number of years ahead of us. People thought that 20 wasn't going to be such a big runner because 28 was so popular. If you look at volumes on 28, 20, and now 16, it's reasonable to expect that volumes and production cycles on 10 and so forth are such that this is going to be a significant era for design-ins and production volumes.
Q: Can you share any more updates on the CoWoS and InFO fronts?
Lee: CoWoS is mature and we're focusing on the ongoing development and rollout of InFO. The first generation of the technology has been qualified. We're qualifying customers’ products based on the InFO technology at 16nm and we're going to be ready for volume ramp in 2016. We're working on our next generation of InFO technology to supplement and complement the silicon scaling of our 10nm technology. Traction is strong. We've engaged lots of customers. We expect InFO is going to contribute a pretty sizable chunk of revenue in 2016.
Q: The deployment of FinFET technology was a huge moment in the history of the semiconductor industry—a big challenge (keeping up with Moore’s Law) met head on. What do you see as the biggest industry challenge in the next five years?
Lee: We're looking at advanced materials, different kinds of transistor technologies. But the immediate next big challenge has to do with continuing the ability to do patterning based on existing light sources. At 10nm, no one is dependent on EUV. We've set up our 10nm technology so that when and if EUV comes on line we can take advantage of it. We continue to work with ASML on EUV tools. The technology itself is very complex. We need to get to a point where there's sufficient wattage and uptime so there are significant wafer volumes.
Q: The design and manufacturing ecosystem that’s formed over the past decade is truly remarkable, I think, in the history of modern business. How do you see the ecosystem evolving in the next five or so years?
Lee: Two things: One's at the macro level and the other at the mega level. We have OIP (TSMC Open Innovation Platform). It has a specific goal: to enable this platform so that between us and our partners we can provide virtually an ASIC-like capability to our customers. That platform is in place. We're looking at extending that to the next level. We'll be doing some stuff that I can't talk about just yet, and we'll see elements start to roll out at OIP Ecosystem Forum this year and continue for the next three to four years.
At a mega level, OIP is part of TSMC’s “Grand Alliance” that our Chairman has talked about. That's a vision, a recognition that it's the combination of R&D of TSMC and its customers together to serve the electronics industry as a whole and keep innovation going. One of the pillars of TSMC's business is we absolutely do not compete with our customers. There are some companies who are dabbling in foundry, but if you look at their core business they're not foundries. In fact, they're probably competitive with their customers. It's the combination of the Grand Alliance of our R&D, our customers' R&D, and our ecosystem R&D, and the joint collaboration that enables all these new products to get to market, products that are not dependent on a completely vertically integrated structure.
Q: So, Suk, gives us the scoop: What surprises will we see at TSMC Technology Symposium?
Lee: You’re going to have to come to find out!
Q: Ha! You drive a hard bargain. We’ll see you there. Thank you for your time.
Lee: See you there, Brian. Thanks!
- TSMC Symposium: EDA/IP Ecosystem Primed for 16, 10nm Nodes
- 2014 TSMC Technology Symposium: Full Speed Ahead for 16nm FinFET Plus, 10nm, and 7nm