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The sixth Cadence Front-End Design Summit may go down as the most memorable, and not just because of the high level of technical presentations and audience participation. The summit fell on the day of the worst storm in Northern California in five years.
Despite the torrential downpour outside, the auditorium was filled to near capacity throughout the day, demonstrating the insatiable hunger for information about all things front-end, from synthesis to verification to test innovations. More than 120 attendees from 59 different companies attended—the highest turnout ever for a Front-End Summit, according to David Stratman, senior product manager for front-end design with Cadence.
“This year’s summit really focused in on our users’ experiences as presented in six customer papers and through a highly engaging panel of experts. It’s clear that interest in the front end of the digital design flow has grown. The presenters did a fantastic job of sharing technical details on their respective designs along with insightful best practices for running Cadence tools like physically aware synthesis, low-power static verification, automated ECO, and test.”
Paul Cunningham, Cadence vice president of R&D, kicked off the summit with a look at trends in synthesis, verification, and test (here is a link to the video of his presentation).
(Note that all video and presentation links require a Cadence.com login; Register now if you’re not already a member of our community).
There are some specific “Dos and Don’ts” when it comes to running physical synthesis, and Ravi Vaidyanathan from Freescale walked the audience through his (here is a link to the video of his presentation and to the presentation slides).
Venkataraman Srinivasagam, technical leader, hardware engineering, with Cisco, offered a deep dive into physical multi-bit cell inferencing for power reduction (here is a link to the video of his presentation and to the presentation slides).
After lunch, Phil Bishop, Cadence vice president of R&D for high-level synthesis, described how engineers can adopt physical synthesis techniques for a more convergent HLS flow (here is a link to the video of his presentation).
Technical events such as the Front-End Design Technology Summit offer engineers an opportunity to share experiences, and Tai Le, senior member of the CAD organization within Atmel, did just that in describing low-power static verification from RTL to tapeout (here is a link to the video of his presentation and to the presentation slides).
Jon Haldorson, principal engineer, Central Engineering Group, PMC Sierra, spoke to the audience about his team’s experiences using hierarchical test features to increase fault accounting accuracy (here is a link to the video of his presentation and to the presentation slides).
And before the panel, Raj Khanna, Soft Machines, talked about using physically aware synthesis on next-generation VISC (Virtual Instruction Set Computing) CPU core blocks (here is a link to the video of his presentation and to the presentation slides).
We rounded out the packed day with a panel of experts, featuring Cunningham, Haldorson, Venkat Ghanta, principal engineer, Cisco Systems, and Leah Clark, associate technical director, Digital Video Technology group, Broadcom. Richard Goering has written about the panel’s highlights here.
Here’s the link to the main Front-End Design Summit archives page.
- Front-End EDA Panel: “Empowering” the RTL Designer