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As the 16nm FinFET node ramps, the potential for engineering productivity gains and design creativity abound, but so too do the challenges.
Engineers from Cadence and TSMC recently laid out many of the 16nm FinFET challenges facing engineering teams today in an hour-long webinar, “Silicon Signoff and Verification: 16nm FinFET Challenges and Features.” They also outlined numerous paths to overcome those challenges.
Hosted by Cadence’s Ruben Molina and Hitendra Divecha and TSMC’s Jason Chen, the webinar covers a range of issues from new rules models and complexities at the 16nm node to solutions in the full RTL-to-signoff flow including Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, and DFM.
Molina, product marketing director for timing signoff with Cadence, notes in the webinar: “At these smaller process nodes, designs are becoming much more complex in terms of placeable instances in the design; there are more mixed-signal components; there are multiple IP cores; complex low-power methodologies.”
“Signoff flows are inefficient due to long runtimes, many loops due to ECOs, and a lack of a convergence solution. At the 16nm node, the design rules are more complex with rules that stress EDA tool performance.”
Chen, a manager in TSMC’s Design Methodology and Service Marketing group, said:
“As process technology advances, the increasing number of design rules and more complex models are affecting almost every single EDA tool, which requires offering richer sets of tool features to satisfy needs."
Divecha, senior product marketing manager for extraction technology at Cadence, said 16nm FinFET poses a tough new challenge for EDA vendors because of “evolving requirements,” which he put in two big buckets: increasing complexity and modeling challenges.
“It’s not just tighter geometries and new rules; it’s about 3D-IC and FinFET. With FinFETs, there’s an explosion in the parasitics and coupling capacitances,” he says.
Divecha, while noting the 5X performance improvement in Quantus QRC Extraction Solution due to its massively parallel compute architecture, in particular calls out accuracy results yielded in the certification collaboration done with TSMC at 16nm.
Correlating against a field solver to achieve certification, results indicated that Quantus QRC didn’t just meet the standards for certification (standards deviation for 2 Sigma within 4% and mean within 1%), it was nearly 2% for 2 sigma and nearly zero for the mean.
“This is industry-leading extraction accuracy,” Divecha said in an interview.
Listen to the complete webinar here.
-- Quantus QRC Extraction Solution – Massive Parallelism Extracts Accurate Parasitics Quickly
-- FinFETs, Advanced Process Nodes, and Parasitic Extraction