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SAN JOSE, Calif.—Trumpeting an industry that “can move the world,” the President and Co-CEO of TSMC unveiled a new low-power process for Internet of Things designs, described expanded R&D process investment, and highlighted the quickening pace of technology introduction in a keynote at the annual TSMC Technology Symposium.
Dr. Mark Liu (pictured, right), addressing an immense convention center room here packed with attendees, credited a collaborative system-design ecosystem for driving innovation into the hands of more and more customers across the globe.
“Our tiny chips can move the world,” Liu told attendees.
He said the industry’s progress in the past several decades is all the more remarkable given the mounting complexity and time-to-market challenges engineering teams face.
“What’s changed is complexity of product design and development. More and more work needs to be accomplished in (a shorter product-development) time frame,” Liu said. That time frame remains roughly on a one-year cadence, but consumers now demand much more functionality, which means more technology innovation must be packed into that time frame.
No mistakes allowed
“IC design and system software complexity have demanded the preparation of the design platform much earlier than before — typically one year earlier. As a consequence, your product design requires much more resources, which means higher design costs. It must achieve first-time success. There is simply no room for mistakes.”
And then, even after you meet the market window, you need to maintain a reliable supply chain, he added.
TSMC continues to respond to help enable system and silicon design, he said, noting significant advances in his keynote address. Chief among them is a new process, 16FFC (16FinFET Compact) , an ultra-low-power “compact version” of 16FF+ technology.
New process disclosed for IoT
Liu said 16FFC cuts power consumption by 50% compared with 16FF+ and offers a nominal voltage of 0.55V—a nod toward power-conscious wearable designs. Version 1.0 design collateral will be available in the first quarter of 2016 with product takeouts expected in the second half of that year.
“Its cost and power reduction advantages can help you meet your mainstream market demands, including mid- to low-end smartphones, consumer products, and wearables and such,” Liu said.
Liu, in an expansive presentation that celebrated the innovation of a number of global silicon-design companies, also called out TSMC’s R&D investment at $2.2 billion for 2015, and capex which could be as high as $12 billion in 2015, an increase of 26 percent over 2014. That is designed to help customers stay on the leading edge of electronics design.
This kind of investment has helped the Taiwanese company speed the pace of technology introduction, he noted. For example, volume production for the 16FF+ process will start in the middle of this year, “one short year” after starting 20nm volume production, Liu said. Customers have taped out more than a dozen products on 16FF+ already, and TSMC expects that to bloom to more than 50 by year’s end, Liu said.
16 FF+ offers 10% better performance than competitive offerings, consumes 50% less total power than TSMC’s own 20nm SoC process, and the company has slashed cycle times per layer 2X compared with its 20nm process, to 0.6-0.7 days/layer, Liu added.
As far as specialty technologies (which as a business for TSMC grew 31 percent in 2014), TSMC boasts the world’s smallest 3- and 6-axis motion sensors and the industry’s smallest SRAM bit cell (with lower noise and leakage) on its 55nm high-voltage process.
For the emerging 10nm node, TSMC has demonstrated yield on a fully functional 256Mbit SRAM. The logic density is 2.1X better than the company’s 16nm node, he added. Risk production is scheduled for Q4 2015 with production volumes following a year later, he said.
Turning process into innovation
This kind of relentless, aggressive development has helped its customers produce some leading-edge designs.
Bob Ragusa, senior vice president of global quality and operations with Illumina, noted how its collaboration with TSMC has enabled much faster and cost-effective genome sequencing.
He noted that the first sequencing of the human genome cost $2.7 billion and took 13 years. Illumina’s goal has been to drive that down to $1,000 per genome sequencing.
“The last step we needed (toward that cost point) was to get what we call a flow cell—basically a patterned MEMs device from TSMC. That allowed us to basically double the information density we could get in an experiment. We were able to combine our DNA sequencing technology with TSMC’s process and manufacturing capability to get to the $1,000 genome.”
Hock Tan, CEO of Avago, described a symbiotic relationship between TSMC and his company that led to a super high-density switch for a networking customer, implemented in 16FF+. The switch has 96 ports, each running 100G Gbps, and drawing less than 2W each. That enables, in a next-generation data center, the tripling of a switch performance to more than 10 Tbps.
“That’s equivalent to downloading over 1 million high-definition Netflix films every second,” Hock said.
To put a finer point on his company’s efforts, Liu said the 4,700 engineers and scientists in R&D helped deliver more than 210 technologies in 2014, supporting 8,800 products from 456 active customers. Its 11 fabs delivered 8.26M 12-inch equivalent wafers.
—TSMC Symposium: New 16FFC and 28HPC+ Processes Target “Mainstream” Designers and Internet of Things (IoT)
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