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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level…

Today we issued a Japan-only press release announcing a high-level synthesis joint…

• 2 min read
High-Level Synthesis , university , TLM-driven design , TLM , japan , SystemC , C-to-Silicon Compiler , DAC 2012 , Aizu , C++

C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with…

• 4 min read
High-Level Synthesis , Flex Channels , C-to-Silicon 12.2 , Jack Erickson , IP re-use , rtl compiler , SystemC , C-to-Silicon Compiler , HLS , clock gating , QoR , System Design and Verification

Securing the Internet of Things

While I had looked at the challenges of hardware/software integration in various…

• 3 min read
security , Intel , device security , hackers , System Development Suite , Amphion Forum , embedded software , Green Hills , burning printer , Mocana , software security , cyber attacks , Internet of Things , phone emissions , Schirrmeister , HW/SW Co-Development

Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly…

• 3 min read
AF , parsing , Specman , Functional Verification , long expressions , e code , e language

Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As…

• 1 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , System Design and Verification , kernel message system , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , kernel messaging system , Andrews

Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to T…

One of the main benefits of moving the design entry point up in abstraction from…

• 1 min read
uvm , TLM , Jack Erickson , Functional Verification , abstraction , webinar , metric-driven verification , SystemC , Watanabe , MDV , System Design and Verification

New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now

Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion…

• 1 min read
ACE , ABV , Joerg Mueller , ABVIP , Mirit Fromovich , ACE verification , ARM , AMBA4

Techniques to Boost Incisive Simulation Performance

Functional verification is the biggest challenge in delivering more complex electronic…

• 3 min read
performance , Accleration , simulation speed , Incisive Enterprise Simulator (IES)

UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented…

• 1 min read
AF , uvm , Specman , Functional Verification , vr_ad , Register Package , e language , UVMe , register enhancements

Optimizing ARM Based Designs for Low Power using Emulation

The month November goes to the Brits, no question. Not only did the James Bond movie…

• 5 min read
ESL Market , Nufront , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Peng Wang , cadence , Acceleration , Functional Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Palladium XP , Emulation , ARM , Schirrmeister , low power optimization

Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are…

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying…

• less than a min read
IEEE 1647 , Specman , Hannes Froehlich , Functional Verification , MOOC , Udacity , training , VA Partners , verification alliance , e language

CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available…

• 1 min read
High-Level Synthesis , video processor , Jack Erickson , CDNLive , System Design and Verification , Freescale , rtl compiler , C-to-Silicon , Israel , SystemC , CDNLive! , DAC 2012 , HLS , ESL

Function Level C Interface – New C Interface for Specman

Working with the conventional Specman C language interface has two major disadvantages…

• 2 min read
AF , Specman , function level , Functional Verification , C Interface , e language , Specman C , TCM , PLI

Creating Custom File Systems and the Linux Loop Device

A few weeks ago we had a crisis at our house. My son managed to delete the data from…

• 7 min read
virtual platforms , Linux loop , File System , virtual prototypes , chroot , System Design and Verification , embedded software , Ubuntu , linaro , custom file systems , mount -o loop , ARM Architecture , Zynq virtual platform , linux , Jason Andrews , Zynq-7000 , simulation

How Many Cycles are Needed to Verify ARM’s big.LITTLE on Palladium XP?

At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar…

• 5 min read
ESL Market , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , Functional Verification , System Design and Verification , big.LITTLE , System Development Suite , embedded software , Palladium XP , Emulation , ARM , cost of ownership

Event Report: Club Formal San Jose – Features and Techniques for Experts, Verification…

Last week over 35 power users from over a dozen companies came together for the latest…

• 5 min read
Incisive Formal Verifier , ABV , Team Verify , Functional Verification , Formal Analysis , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Chelsio , Chris Komar , apps , assertions , Club Formal , bypass logic verification , IEV , Oski , Formal verification , IFV , liveness , Assertion-based verification

Ubuntu 12.10 on a Virtual Platform at ARM Techcon

Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center…

• 1 min read
ARM Techcon , Virtual System Platform , virtual platforms , programmer's guide , virtual prototypes , Cortex-A9 , Cortex-A , VSP , Ubuntu , ARM , Quantal Quetzal , Ubuntu 12.10 , linux , Jason Andrews , Zynq-7000

Margins are Costly - Don't Let Them Grow Out of Control!

Last week, Professor Jan Rabaey of the University of California at Berkeley gave…

• 2 min read
High-Level Synthesis , Low Power , Rabaey , low power summit , margins , rtl compiler , variability , C-to-Silicon Compiler , HLS

Changing the Game with Processor Based Emulation

I have always been fascinated by game changing moves. Some are more successful than…

• 7 min read
RPP , FPGA Based Prototyping , prototyping , cadence , Acceleration , debug , Functional Verification , System Design and Verification , Palladium , System Development Suite , embedded software , Emulation , Software Development and Debug , Rents Rule , Schirrmeister , system integration , FPGA

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog…

• 1 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , Functional Verification , OVM , e , webinar , UVM ML , multi-language , Accellera , SystemC , multi-language UVM , IES , IES-XL

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher…

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose…

• 3 min read
coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , webinar , Incisive Enterprise Verifier , Chris Komar , enriched metrics , MDV , IEV , debugging , John Brennan , simulation , Formal verification , IFV

Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their…

• 3 min read
AF , indexed ports , SystemVerilog , stub files , Specman , stubless indexed ports , Functional Verification , ports , Nir Hadaya , SV , e language , interface , simulation , Avi Farjoun

Shameless Promotion: Free Club Formal San Jose (with Lunch) on Wednesday 10/17

Please join Team Verify and other design and verification engineers at the next …

• 1 min read
ABV , Formal Analysis , formal , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , Club Formal

iPhone5 Differentiation is Chip Design

In case you may have missed it, Apple recently launched a new iPhone. As per the…

• 5 min read
High-Level Synthesis , Apple , TLM , RTL , android , iPhone5 , Samsung , SoC , C-to-Silicon , software , smartphones , ARM , ESL , iPhone , Audience

Using a Network File System with the Xilinx Zynq-7000 Virtual Platform

There are a number of ways to do embedded software development for Xilinx Zynq-7000…

• 5 min read
Ubuntu 12.04 , Zynq virtual platform , Network File System , Embedded Linux

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Earlier this year, Cadence announced the expansion of its VIP Catalog to include…

• 2 min read
validation. , Driver , firmware , System Design & Verification

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study…

Right up there with functional verification, the challenges of low power design and…

• 3 min read
uvm , Low Power , GoPro Hero2 , thermal verification , Functional Verification , MCAD , video , mechanical design automation , EDA , low-power design , thermal behavior , heat dissipation

UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation…

• 2 min read
AF , uvm , Specman , BFM , Testflow , Functional Verification , testflow phases , e language , team specman , sequences , Reset mechanism , Shneydor , verification , sequence driver
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