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Today, I will discuss some alternatives for chip-level verification with designs that have microprocessors in them. Since I started at Axis Systems back in 2001, the number of designs with processors has steadily gone from a few, to some, to most, to nearly all. Not only do most chips have processors, many have more than one.
This makes a nice test to use for verification and to reuse on the FPGA board or final silicon to make sure basic DMA operations work correctly. The first thing a verification engineer notices about the test is that it is very deterministic. The test will not really exercise any interesting corner cases. The addresses, the data, the size, the modes, and the timing are fixed by the test writer and hard coded into the test.
In future blog entires I will provide more insight into how ISX provides communication between a test bench and C test functions and variables running on an embedded processor to improve verification, but if you are really interested and cannot wait I recommend you can attend CDNLive! next week in San Jose.
Three ISX users will present ISX verification stories, and one of them started with a library of directed C tests running on an ARM processor and ended up with an environment that provides the ability to vary the tests using constraints and improve verification. Look for session 1FV5 "Using ISX to Build a Constrained-Random Test Environment from Directed C-Based Tests" on Tuesday afternoon.
Questions? Comments? Post below.