Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Before I dare take a stab at adding to the many predictions already made for 2009 (like those in EE Times and SCD Source), allow me to share with you some of the main verification technology-specific observations that the "Trailblazer" team saw in 2008:
1 billion logic gate chip roadmapsAs noted in a previous post, SoCs with over 1 billion logic gates are now on the drawing boards of customers around the word. (That's billion with a "B", which per the 6x rule of thumb implies they will have 6 billion transistors.) Of course, no customer in their right mind would ever create such a monster gate-by-gate from scratch. Instead, such designs will be comprised of many, many blocks of proven IP. However, as many customers have learned the hard way when re-using "proven" IP in new chips, it's inevitable that once unreachable / masked corner-case bugs suddenly appear in this proven IP for a whole host of reasons. Long story short: the requirements for verification tool and methodology scalability to simply re-validate these new IP collections, let alone root out the new corner-cases, are daunting to say the least. (And FWIW, I remain surprised this whole "billion gate verification scalability" issue isn't getting more attention in the mainstream trade press, and/or when it is mentioned at all it's only raised in terms of the physical design challenges of the 22nm node).
True "Metric Driven Verification" (MDV) starts to evolve from CDVIn 2008 many customers have started to add new metrics above and beyond the recording of code and functional coverage. Assertion coverage, sequence coverage, firmware code coverage, and the man-hours of D&V personnel are all examples of data points that engineers and managers at our most advanced customers are collecting together with [brace yourself for a shameless product plug] Incisive Enterprise Manager to get a complete picture of a given project's progress. In all honesty, this is not just a 2008 trend -- it's been ongoing for few years now, and it's been so prevalent that it inspired the creation of the new "Enterprise Planner" capability in Enterprise Manager. (And in the "imitation is the sincerest form of flattery” department, 2008 saw Mentor soft launch their pale Enterprise Manager clone. For completeness sake: last I heard, Synopsys' clone is still on ice due their obsession with propping up VMM. But I digress.)
The "language war" is over -- all languages won!Given the growing popularity of the SystemVerilog language, in 2008 I saw many customers trying to "standardize" on using SystemVerilog as their only verification, ESL, RTL, and assertions language (as per the language's original promise). While this plan still has an obvious conceptual appeal, with very few exceptions customers have found this to be practically impossible to implement in practice.
In short, if they haven't already realized it, customers are discovering that it's a multi-language world whether they like it or not. Note: I'm not suggesting that SystemVerilog has not been widely adopted, and that some customers will use it for most of their work. Instead, people are coming to terms with the fact that a) SystemVerilog is not a verification paneca, and b) there is a ton of non-SystemVerilog IP - both legacy code and new VIP -- that will need to be leveraged now and forever. In summary, SystemVerilog is simply a great complement to all the other EDA tools and methodologies people already have, and/or need to adopt in addition to SystemVerilog itself.
Pre-silicon HW/SW co-verification became too important to ignoreMy colleague Jason Andrews expertly covers this topic in his blog, so I will simply refer you to his latest post on this issue.
Analog+Digital verification frustration growsI cover this observation in my November post on the DV Club lunch presentation from Dr. Henry Chang of Designers' Guide Consulting. To briefly recap: I was "relieved" (in an ironic, negative sense) to hear that an expert like Dr. Chang is seeing that the analog verification is still 15-20 years behind digital verification methodology and levels of automation, and for various reasons the situation is improving slower than anyone likes.
And last but not least:
Low Power pain continuesI'm sure it's no surprise that low power D&V was an ongoing concern in 2008. Let me share a relevant anecdote: at every "ClubT", techtorial, or on-site customer meeting, I always ask the audience 2-3 questions about what pain points they may be facing to get a sense of how to further tailor my remarks to their information needs. When ever I ask, "is power consumption and/or low power D&V an issue with you?", 95% of the hands in the room go up every time.
I'm eager to hear your reaction to these observations, so feel free to post some comments below or contact me offline.
Finally: Happy New Year!