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Over here at Cadence we were pondering the same question and
started by estimating the world wide verification community at 15,000
engineers. My colleague Joe Hupcey and I
arrived at that number by doing some calculations based on the number of
verification licenses we have, the EDAC numbers, and a bottom-up customer
analysis. We focused on engineers using
HVLs to separate the design and verification communities. Our next step was to objectively split that
community based on OVM and VMM usage and what we came up with supports Harry's methodology
10,000 of the 15,000 verification engineers are using the
OVM with SystemVerilog and eRM with e. The 10,000 splits into roughly 6000 on the OVM
(based on the number of engineers registered with the OVM World now) and 4000 eRM
users (based on the e users in the Team Specman blog, the Specman Yahoo group, and
the others below). We can combine these
to 10K because both eRM and OVM implement the same methodology - a methodology with
proven reuse for several years and across thousands of projects and the broadest, deepest VIP portfolio. If we assume the rest of the verification
engineers are using VMM and legacy Vera/RVM, then we roll-up to the same 2:1
ratio as Harry.
These tough economic times can make it hard to make resource
decisions. With 2:1 odds favoring the OVM, at least the verification
methodology decision is clear!
So where are you placing your bets?
Additional e communities: IEEE 1647 working
group, Avidan Efody's "Specman Verification" site, Yaron Ilani's "Think
I guess I see the public side of the momentum in pretty simple terms. Last year at this time, the majority of the SystemVerilog users were on VMM and now they are on the OVM. When we start to consider how verification IP flows in the ecosystem, this majority is likely to start swaying VCS users. Synopsys has publicly stated that they can't run it, but we've seen some posts on the OVM World from users to the contrary.
Its the private side that we are starting to see customers migrate from VCS/VMM to Incisive/OVM. One year is a pretty short time, so those success stories will start to become public this year. One of those stories comes from Adaptive Chips and you can read that in my blog post from earlier this week. www.cadence.com/.../adaptive-chips-selects-ovm-over-vmm-an-interview-with-amjad-qureshi.aspx You'll start to see more of these coming out shortly.
Another point to note is that the test bench methodology alone is no longer sufficient to verify today's SoC. User need other solutions that complete the verification environment like metric driven verification using planning and management software and verification IP. In both of those areas, Cadence provides leading edge technologies that are tightly integrated with the OVM, not VMM. Technologies like those are also inflection points increasing the momentum to the OVM.
So for me, the momentum is the rapid rise of OVM in the Mentor and Cadence bases as you've stated, but also the leading indicators that it is affecting VCS users as well. The interesting thing for us to watch will be how that momentum reshapes the verification ecosystem in 2009.
I'm not sure I see the momentum that you are referring to. If you assume that (1) all customers previously using the Cadence simulator were to adopt OVM, that (2) all the Mentor users move to OVM, and (3) all the Synopsys users move to VMM, you'd end up with this 2:1 ratio just based on the previous market share (which was pretty evenly split 3 ways). That is, there is no real evidence in the numbers that very many customers switched from VCS to Questa or IUS just to use OVM, or vice versa. Rather, it seems that the majority of customers stayed with what they previously used for their simulator. That sounds like stagnancy, not momentum.
Thanks for the detailed analysis! Sounds like we are on the same page -- more folks voted for OVM than VMM. Our exuberance comes from the fact that in one year the OVM has gathered enough momentum to do so well in your survey. These surveys are great for the whole industry. Thanks for the effort -- clearly it took a lot of work -- and let's see if we can get all of the bloggers together at DVCon as JL suggested.
Since conducting the Verification Methodology Poll and publishing the raw results last week, I've been planning to follow up with a post that digs a little deeper into the numbers. Things have gotten rather busy in the meantime, both at work and with organizing the SaaS and Cloud Computing EDA Roundtable for next week at DVCon. So I've let it slip a little.
Well, I noticed today that the verification methodology poll was referenced in this blog post. The results were somewhat mis-interpreted (in my opinion), so here are my own interpretations to set the record straight. You stated:
"According to the poll conducted by Harry Gries in his Harry the ASIC Guy blog, you should go 'all in' on the OVM because it is the 2:1 favorite."
In fact, the raw results had VMM with 80 users and OVM with 125 users, a ratio of just over 1.5:1 (1.5625 to be exact). So the 2:1 ratio is not accurate. However, if you add in RVM/Vera users to the VMM numbers, and then add in AVM, eRM, and e users to the OVM numbers, that ratio is more like 1.8:1. Closer, but still not 2:1.
It also indicates that my poll says that "you should go 'all in' on the OVM". I never said that nor does the poll say anything about what you "should do". The data simply captures what people are planning on using next. If you are inclined to follow the majority, then perhaps OVM is the way to go. By contrast, there is nothing in the poll comparing the technical merits of the various methodologies. So, if you are inclined to make up your own mind, then you have some work to do and my poll won't help you on that. You're probably better off visiting JL Gray at Cool Verification.
No poll is perfect and it will be interesting to compare to DVCon and John Cooley polls to see if they are consistent. Here are a few other interesting stats that I pulled out of the poll results:
* 91% of respondents are using some sort of SystemVerilog methodology
* 10% are using both OVM and VMM (although I suspect many of these are consultants)
* 27% are still using e or Vera (more e than Vera)
* 4% are using ONLY VHDL or Verilog (this number may be low due to the skew of respondents towards advanced methodologies)
Again, I welcome you to download the raw data, which you can find in PDF format and as an Excel workbook, and draw your own conclusions.
harry the ASIC guy