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For those Specmaniacs using the REAL number data type & ports capabilities in Specman, you might be interested in a webinar our analog colleagues are hosting tomorrow (June 10) from 07:00- 8:15 AM (PDT) and a second broadcast at 10:00 -11:15 AM (PDT). Specifically, the webinar is titled "How to Boost Performance for Mixed Signal SoC Top-level Verification", and it will address how to handle mixed signal design complexities that can create additional re-spins due to logic and functional errors, interconnect errors, polarity inversion errors, etc. The presenters will also show how some new REAL digital modeling capabilities can be used to perform top level verification to achieve significant simulation mixed analog & digital domain performance improvements. Here is the link to sign-up:http://www.secure-register.net/cadence/virtuoso_webinarsAnd here is a more detailed outline of the presentation:* Cadence Mixed Signal Verification solutions addressing the analog and digital centric use models* What is Real Number Modeling? * Simulation performance vs. accuracy tradeoffs with real/wreal models* Basic and Advanced real/wreal functionality included in the IES 8.2 release* Detailed examples of Wreal Models, e.g. PLL, VHDL DAC, Analog Mux, etc. * e & SystemVerilog Real to Electrical connections* Provide examples of real to wreal coercion, wreal arrays, how to effectively develop a wreal table model, etc.
Hope to see you online!