Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009). In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of logic, but the high-end SoCs -- represented by product families such as the Xilinx(R) Virtex(R)-6 and Spartan(R)-6 -- are growing fast. That is exactly the type of design we've targeted with the Incisive Enterprise Verification solution and the OVM.
Cadence and Xilinx are working to simplify the development of these complex SoCs by applying the Incisive solution to the newly announced Xilinx Targeted Design Platforms. There are two significant parts of the announcement -- collaboration around new, high-performance, standards-based simulation libraries and application of the OVM for SoC FPGAs.
The first point represents significant engineering work to move away from the proprietary packaging that Xilinx used to the new IEEE standard encryption championed by Cadence. The new encryption standard was originally donated by Cadence and is now part of the SystemVerilog (1800), Verilog (1364), and VHDL (1076) standards. Cadence chairs this standards effort and was able to help Xilinx adopt the technology and prove it in common customers. The result is an average 2X speed-up for simulation, with some users experiencing still higher performance. Watch this blog for a team genIES explanation of this compelling new standard.
The second, and possibly more significant, point is the recognition that the OVM is an ideal choice for SoC FPGAs. These FPGAs typically depend on standard protocols -- on-chip bus and interface protocols -- and reuse of both vendor-supplied and user-created VIP. Furthermore, these FPGAs are scaling to the point where users need to break with the traditional "burn-and-churn" FPGA methodology and adopt the more comprehensive, metric-driven methodology applied to ASICs of the same size and complexity.
For all of you who have been looking for more FPGA verification content from Cadence, look at this announcement as just the first with more to come. If you have any requests in the FPGA space, please feel free to comment here or contact me at email@example.com.