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Some background info:
Taking a quick look at Power dissipation in CMOS:
Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture power intent. For details refer to “A practical Guide to Low Power Design” – download a copy at http://www.powerforward.org/
So, how to deal with parts of the design that can not be powered down during the operation of the chip? Some examples are – processor cores, and other dedicated applications that have variable computing needs, but do remain to be always on.
A practical solution:
One of the primary techniques used in the industry is DVFS – Dynamic Voltage and Frequency Scaling which consists primarily of:
DVFS is used for both:
In this blog, I will primarily focus on Frequency scaling and how to effectively simulate that in the context of SoC level simulation. Later blogs will focus on Voltage Scaling.
Some more background info:
In order to simulate Analog elements in the SoC we need a way to simulate Analog behaviour at digital speeds so that system-level simulations containing both analog and digital components can be performed. Cadence has introduced a digital centric mixed signal verification environment – Digital Mixed Signal (DMS). This new verification environment targets customers using digital centric use models. It refers to – but is not limited to – mixed signal verification using digital simulators only. In other words, it delivers capabilities to verify the mixed signal design using digital centric methodologies. This is effectively done by using Real Valued Modeling (RVM) where speed is traded off for very high level of accuracy typically involved with simulation of analog elements.
RVM is a mixed approach, borrowing concepts from analog and digital simulation domain. The values are continuous, floating-point (real) numbers, as in the analog world. However, time is discrete, implying that the real signals change values based on discrete events. In this approach, we apply the signal flow concept so that the digital engine can solve the RVM system without support of the analog solver. This guarantees a high simulation performance in the range of a normal digital simulation and orders of magnitudes higher than the analog simulation speed.
There are four different language standards that support RVM, namely:
It is important to note that the real-wire (wreal) is defined only in the Verilog-AMS LRM. Thus, a wreal can be used only in a Verilog-AMS block. However, it is only the digital kernel that solves the wreal system. There are no performance drawbacks when using these types of Verilog-AMS modules in a digital simulation context.
Here’s an example of using wreals for creating a VCO model that is used to control clock speed and can be effectively used for dynamically scaling of frequency to verify dynamic power management.
In this example, two VCOs are instantiated to independently generate clocks for the DSP and MCU blocks in the design. Depending on processing needs, the clock speed is independently controlled from an on-chip controller – see waveforms..
vco vco_mcu (.vin(vco_vin_mcu_clk), .clk(mcu_clk));
vco vco_dsp (.vin(vco_vin_dsp_clk), .clk(dsp_clk));
The control logic on the chip runs the design units DSP & MCU in this case, at the slowest possible speed in order to conserve dynamic power. Details of the control mechanism are left out and can form the basis of another blog.
The effects of dynamic frequency scaling on system performance and throughput can be effectively measured and verified using this simple approach.
Stay tuned for more...