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Recently our colleagues on Team ESL announced a new TLM-Driven Design and Verification Solution. Team Specman guesstimates that about 15% of Specmaniacs are already using Specman with SystemC and/or some form of transaction-level modeling (TLM) flow. For those of you that are in this camp, a logical question is "what's new"? In advance of DAC (and the ClubT's this fall, and more detailed follow-up blog posts), at the 10,000ft level:
* There are enhancements being added to Specman/Incisive Enterprise Simulator-XL to simplify the TLM-verification flow with SystemC. Specifically, look for new hooks to support TLM/RTL metric-driven verification in general, and new source level debug visualization capabilities in SimVision.
* The methodology & product docs will have new content on how to perform multi-language OVM-based functional verification of pure TLM, TLM/RTL, and RTL. The subtle point here is the reference to eRM, er, we mean *OVM*, where OVM == easy, structured re-use -- i.e. Team ESL is working to extend the benefits of OVM into TLM verification IP.
* For those Specmaniacs that are regularly asked to pull double-duty as design and verification enginers, you will appreciate how this solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability.
Message for the other 85% of Specmaniacs doing pure RTL today:All we [Team Specman] can say is that we have seen the aforementioned 15% of ESL/TLM using Specmanics enjoy some to all of the benefits being claimed for the ESL-centric flow vs. a traditional RTL flow. In short, this stuff really is worth a look.
Finally, it's important to note that from the "purely Specman point of view", to some extent Team Specman is actually neutral about the whole RTL vs. ESL/TLM discussion. Why? Recall that Specman does not care about the format of the DUT that it's verifying -- e/Specman was created to be a generic verification solution, period. Hence, as many of you know (because you do it every day) with Specman you can verify DUT made of single-language RTL, multiple RTL languages, TLM/RTL, all TLM, plain vanilla SystemC, RTL+embedded software, HDL+AMS models -- Specman doesn't care. The point in the context of this ESL/TLM news is that regardless of whether you stick with RTL or move to TLM, you can reuse your e/Specman testbenches and eVCs. Truly this flexibility is another benefit of e/Specman in addition to AOP, the safe "infinity minus" approach to generation, ... we could go on ;-)
Reference links:The official PR: Cadence Introduces First TLM-Driven Design and Verification Solution to Increase Engineering Productivity over RTL-based Flows
Great article from fellow Blogger Richard Goering on how "TLM Brings “ESL” Down To Earth"
More details from fellow blogger Steve Brown: "TLM-Driven Design and Verification Solution"
Recall that sequences are part of OVM -- both OVM for e and as well as OVM for SystemVerilog. The Incisive documentation has a lot of information and examples on creating OVM-compliant sequences in both languages, and the OVM docs posted at OVMWorld.org are another great resource:
How to build sequence in systemverilog like E.