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I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin!
10. VHDL 1076-2009 Support. Huh? How did this get here? Given the breadth of IES (Incisive Enterprise Simulator) use across the industry we have requirements from every imaginable source so calling out VHDL is a great example of that breadth. Simply said, reuse is king and there is a huge amount of VHDL out there. The only thing to challenge on-going VHDL use is the movement to higher abstraction.
9. SystemC Beats SystemVerilog for Design. Is this heresy from Sherilog (or is that Sheresy? Or ShererC?) Oh contraire mon frère, this move up abstraction is as much due to the fact that software is a critical function of the design as the fact that the designs are getting to big to manage. SystemC is just more natural language choice for mixing hardware and software.
8. OVM is Accelerated. Designs are just getting HUGE which means hardware must grow as an important part of SoC verification. OVM will be accelerated by continuing improvements in the Incisive Enterprise Simulator, but for a really big jump, moving to the Incisive Palladium Series is a must.
7. Yankees Verified to Reuse World Series Win in 2010. ‘nuff said there.
6. Digital Mixed Signal (DMS) Makes Verification Real (pun intended). Analog is analog. No amount of speed-up is going to get transistors or analog behavioral running at digital speeds. That’s what makes digital digital. DMS, as a part of MSV (mixed-signal verification), is a way to get the best of both worlds. And this prognostication comes from a guy who wrote analog mixed-signal simulators for Analog Devices a million years ago.
5. Power-aware Every Minute of Every Day. If you’ve been living on an island – be it design, verification, or implementation – swim to our shore. We’ve got the only fully connected power-aware solution throughout the entire project process, including enterprise management. The island life may have seemed nice in 2009, but when you do real projects in 2010 you’ll quickly realize you need to be power-aware all of the time.
4. e Continues to Grow. Grow? Yes! If only I could share numbers with y’all. By doing what we do best – creating multi-language solutions – we have invigorated the already vibrant IEEE 1647 e user base. e continues to be the SoC verification language of choice in 23 of the 25 biggest SoC houses. With the SystemVerilog world coalescing around OVM (see #1), verification teams will be using a common methodology freeing them to choose the best language for their projects. It is, and always has been, a multi-language world.
3. Debug, Debug, Debug – Damn, Where is the Bug! I believe that verification is single-handedly supporting the storage market with the amount of data we create.With proliferation of OVM, the amount of data -- both coverage and signal/transaction based -- is growing even faster than before. Advances in Metric Driven Verification (MDV) and traditional debug will be needed to keep up.
2. Cadence Verification Performance. We have the best performance solutions and know-how from single simulation runs to full projects. Our inventions range from native-compiled simulation, to scalable processor-based hardware solutions, to enterprise management. And we’ve got more to come!
1. OVM is standardized. Accellera VIP TSC is working on this very subject, and the OVM numbers are overwhelming. 50,000+ downloads from OVM World and nearly 10,000 registered users. Openness got the OVM started in 2008 and 2009 saw SystemVerilog support among the simulation vendors reach a common point that enabled universal OVM adoption. However, it is the industry’s leading technology sustains the growth of the OVM and will continue to do so in 2010.
Let the comments flow and I’ll be happy to discuss my top 10. If we don’t get to talk, email, blog, or tweet, let me take this momemnt to wish you a happy and a merry and a healthy 2010.