Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin!
10. VHDL 1076-2009 Support. Huh? How did this get here? Given the breadth of IES (Incisive Enterprise Simulator) use across the industry we have requirements from every imaginable source so calling out VHDL is a great example of that breadth. Simply said, reuse is king and there is a huge amount of VHDL out there. The only thing to challenge on-going VHDL use is the movement to higher abstraction.
9. SystemC Beats SystemVerilog for Design. Is this heresy from Sherilog (or is that Sheresy? Or ShererC?) Oh contraire mon frère, this move up abstraction is as much due to the fact that software is a critical function of the design as the fact that the designs are getting to big to manage. SystemC is just more natural language choice for mixing hardware and software.
8. OVM is Accelerated. Designs are just getting HUGE which means hardware must grow as an important part of SoC verification. OVM will be accelerated by continuing improvements in the Incisive Enterprise Simulator, but for a really big jump, moving to the Incisive Palladium Series is a must.
7. Yankees Verified to Reuse World Series Win in 2010. ‘nuff said there.
6. Digital Mixed Signal (DMS) Makes Verification Real (pun intended). Analog is analog. No amount of speed-up is going to get transistors or analog behavioral running at digital speeds. That’s what makes digital digital. DMS, as a part of MSV (mixed-signal verification), is a way to get the best of both worlds. And this prognostication comes from a guy who wrote analog mixed-signal simulators for Analog Devices a million years ago.
5. Power-aware Every Minute of Every Day. If you’ve been living on an island – be it design, verification, or implementation – swim to our shore. We’ve got the only fully connected power-aware solution throughout the entire project process, including enterprise management. The island life may have seemed nice in 2009, but when you do real projects in 2010 you’ll quickly realize you need to be power-aware all of the time.
4. e Continues to Grow. Grow? Yes! If only I could share numbers with y’all. By doing what we do best – creating multi-language solutions – we have invigorated the already vibrant IEEE 1647 e user base. e continues to be the SoC verification language of choice in 23 of the 25 biggest SoC houses. With the SystemVerilog world coalescing around OVM (see #1), verification teams will be using a common methodology freeing them to choose the best language for their projects. It is, and always has been, a multi-language world.
3. Debug, Debug, Debug – Damn, Where is the Bug! I believe that verification is single-handedly supporting the storage market with the amount of data we create.With proliferation of OVM, the amount of data -- both coverage and signal/transaction based -- is growing even faster than before. Advances in Metric Driven Verification (MDV) and traditional debug will be needed to keep up.
2. Cadence Verification Performance. We have the best performance solutions and know-how from single simulation runs to full projects. Our inventions range from native-compiled simulation, to scalable processor-based hardware solutions, to enterprise management. And we’ve got more to come!
1. OVM is standardized. Accellera VIP TSC is working on this very subject, and the OVM numbers are overwhelming. 50,000+ downloads from OVM World and nearly 10,000 registered users. Openness got the OVM started in 2008 and 2009 saw SystemVerilog support among the simulation vendors reach a common point that enabled universal OVM adoption. However, it is the industry’s leading technology sustains the growth of the OVM and will continue to do so in 2010.
Let the comments flow and I’ll be happy to discuss my top 10. If we don’t get to talk, email, blog, or tweet, let me take this momemnt to wish you a happy and a merry and a healthy 2010.