Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
In the numerous tweets, blog posts, and online forum discussions on the upcoming Universal Verification Methodology (UVM) standard from Accellera, I have seen a couple of references along the lines of "UVM=OVM+VMM" and that really concerns me. It concerns me because it's not accurate, but it concerns me even more because the very idea doesn't make sense.
Note that the Accellera decision was specifically to make the OVM the base for the UVM, with the expectation that additional features would be added on top of this base for future UVM releases. It is quite possible that some of the additional features may be derived from VMM as well as from OVM World contributions, but the UVM as it exists and is defined today is the OVM, not OVM+VMM.
So am I just splitting hairs here? I don't think so. There is a lot of overlap between the baseline features of the OVM and VMM, and any attempt to try to create some sort of "OVM+VMM" Frankensteinian hybrid would likely be a disaster. Either functionality would be duplicated to try to make it familiar to users of both methodologies or it would end up as a third methodology, satisfying no one.
Accellera did the right thing by choosing the OVM as the base for the UVM. I urge the committee to release a UVM 1.0 as soon as possible, fully compatible with OVM 2.1, and to maintain backwards compatibility in future UVM releases as new features are added. This will ensure that the 10K registered users at OVM World and all their colleagues have a painless transition to the UVM.
Keeping the UVM fully backwards-compatible with the OVM benefits VMM users as well. Recall that the first stage of the Accellera VIP effort was to define a library for OVM-VMM interoperability. This library provides VMM users a clear path to the OVM without having to recode all their VIP, so ensuring that UVM=OVM will provide VMM users a clear path to the UVM standard as well.
The truth is out there...sometimes it's in a blog.