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More and more often it takes a village to achieve verification success. As reported recently by MathWorks, Harris pulled together technology and support from Cadence, MathWorks, and Xilinx to cut their verification time by more than 85% and achieve a defect-free FPGA implementation.
“EDA Simulator Link provided a direct co-simulation interface between our
MATLAB model and our logic simulator, which enabled us to verify our
design earlier, identify problems faster, complete more tests, and
compress our entire development cycle," said Jason Plew, Harris Corporation. EDA Simulator Link is a co-simulation interface that enables the use of MATLAB or Simulink with Cadence Incisive verification tools. The capability is consistent with the top-down design and verification principles discussed in the new Cadence EDA360 vision paper.
Why the need for better verification?
Harris engineers were consuming significant effort verifying their FPGAs but still only achieving 30% test completion prior to their deadlines. When they examined their process, the realized that their manual process involved exporting large amounts of data for each change resulting in an 8-hour fixed-cost for each debug cycle.
By expanding the verification view beyond simulation, Harris engineers were able to leverage new technology from MathWorks to both reduce the fixed-cost to under 1 hour and parallelize their verification runs on their regression farm. As a result, they cut their verification time by more than 85%, were able to run 100% of their tests, and achieved a defect-free FPGA implementation.
What is your verification story?
Project teams like this one at Harris have to look beyond traditional means to integrate solutions from multiple providers to achieve success. There are a lot of stories like this one, so feel free to contribute your story here and watch this space for more EDA360 related verification.