Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design"; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners. Specifically, quoting this document:
"EDA360 helps close the profitability gap [i.e. the difference between what you can make, and what you can make money on] through integration ready IP-creation, IP integration, and optimization. Given that embedded software can take up half the cost of SoC development, EDA360 also supports hardware/software integration and verification. It thus expands the scope of EDA well beyond its original boundaries."
Sound familiar? This statement should resonate with many of you, since Specmaniacs and Trailblazers like you were the ones that inspired it! Furthermore:
EDA360 supports three important capabilities: System Realization is the development of a complete hardware/software platform that will provide all necessary support for end-user applications ... SoC Realization is the completion of an individual SoC (or alternative packaging choice, such as 3D IC). Along with the integration of silicon IP developed through Silicon Realization, SoC Realization includes "bare-metal software" such as drivers and diagnostics. ... Silicon Realization represents everything it takes to get a design into silicon ... an analog or digital IP block for an SoC, an IP subsystem, or a complete IC without embedded software.
So here is the $64 question: how does Specman and e relate to all of this? What follows is Team Specman's take on this question (we're very eager to hear your thoughts - please comment below, or speak to us at DAC and other forums!). For starters, we need to take a quick step back to the original design philosophy behind the e language itself.
Generic Verification Platform
When the e language was created it was specifically designed to be a generic verification platform. That is, e testbenches are specifically designed to be totally independent of the format of the DUT. Specman (whether stand-alone or as part of IES-XL) has faithfully implemented this philosophy, where we've had customers connect up DUTs comprised of Verilog, SystemVerilog, VHDL, C, C++, SystemC, Matlab, AMS models, pure SPICE models, Xtreme and Palladium systems, FPGA prototypes, post-silicon boards, test instruments, and countless simultaneous combinations of all of the above.
The reason for this flexible approach should be obvious to any verification professional: in a nutshell, you just never know what the designers are going to throw at you. Additionally, e's creators realized that they could not predict what design formats and permutations would withstand the test of time. Thus, to insure that e would be relevant forever, they deliberately made it a generic solution with unrestricted extendibility (see: "Aspect Oriented Programming", or "AOP")
When you compare e/Specman's design philosophy to the three levels of EDA360 -- System Realization, SoC Realization, and Silicon Realization -- it should be apparent that e/Specman is a relevant verification solution for all three levels of abstraction. Indeed, beyond the many users of e/Specman at the "Silicon Realization" level, with the introduction of Incisive Software Extensions and the transaction-based acceleration support introduced for Xtreme and Palladium several years ago, we have seen more and more customers use e/Specman at the SoC Realization level. Of course, as ESL solutions like C-to-Silicon and the Palladium XP verification computing platform continue to prosper; we expect this trend to snowball.
That said, despite having a platform that's compatible with any type of verification, there is one significant operational requirement that's critical to address. In order to support verification at ever higher levels of abstraction, the given verification solution has to be within an order of magnitude of the DUT's wall clock speed. Anything less will not suffice.
Team Specman is well aware of this challenge, and we are tackling it head on. As many of you will see in this year's "ClubTs" and other events, improving Specman's wall clock performance (and its evil twin, memory consumption) to support the high-throughput verification that these higher levels of abstraction require is at the core of the Specman development roadmap. Specifically, a Specman "Advanced Verification Option" is planned for the next release that will leapfrog over your current regression simulation run times to provide you considerable verification time savings.
Serving IP Integrators
But what about the emerging class of pure "integrators?" The EDA360 vision paper cannily observes that:
"Some innovators will redefine themselves as integrators. They will integrate at the silicon, SoC, and system levels. They will make heavy use of externally designed silicon and software intellectual property, they will tend to stay at mature process nodes, and they will invest heavily in embedded software development. They will become application-focused platform providers, not 'chip' providers."
As Mike Stellfox wrote in a recent blog post on the "UVM - 10 Years in the Making", from the beginning eRM was, and now UVM is, all about creating integration-ready Verification IP. It bears repeating that the key methodology concepts that are delivered by UVM include:
By adhering to these principles, Verification IP creators are assured to give the IP integrators the modular, reusable, scalable, machine controllable, "plug and play" verification platform they must have in order to be successful.
Finally, whether it's in the Comments section below, on Twitter, on Facebook, or at the many events throughout the year (like at the upcoming DAC, June 14-17 in Anaheim, CA); Team Specman is eager to hear your feedback on EDA360, its relationship to your verification challenges, and how you see e/Specman serving you today and for all time.
Joe Hupcey IIIFor Team Specman
P.S. The philosophy of taking a generic approach to verification challenges is carried through to other aspects of the e language. One example is the e language's "infinity minus" approach to stimulus creation. Assuming advance knowledge of where errors exist is one of the leading causes of verification failures. Thus, all stimulus to the DUT is randomized unless otherwise specified so you can unearth unimagined side-effects and bugs.
I am using Specman e v6 with NCVerilog.
I worked on NCVerilog.
Now I want to learn how to interface NCVerilog with Specman.
Where can I get good user manual or tutorials for same ?