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Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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Mark your calendar and sign up for the two upcoming free verification sessions sponsored by Cadence. Space is limited. So, please sign up today!
All-Day, Hands-on technical workshop in Irvine, CA
Topic: Advanced Verification Techniques using e/SV Workshop
Learn how to architect an advanced testbench using OVM/UVM that contains generation, coverage and checking and much, much more.....
This workshop will focus on introducing attendees to advanced verification techniques using the latest in verification languages. The user will learn first-hand, through on-the-fly coding by the presenter, how to architect an advanced testbench using OVM that contains generation, coverage and checking. Specman and e will be used for the modeling; however, comparisons to SystemVerilog will be made throughout. The attendee will also understand how easy it is to link the coverage collected in the testbench to specific sections of an executable verification plan (based on MS Word or another common documentation format) to track coverage results throughout the life of their project.For more details, see https://www.secure-register.net/cadence/incisive_workshops
On-line Webinar on your Desktop
Topic: Apples vs. Apples HVL Comparison Finally Arrives
Choosing the Right Verification Language Webinar
Over the past few years, the discussion of hardware verification languages (HVLs) has come full circle. At first, verification teams tried to assess the strengths and weaknesses of individual language features with the goal of creating their own verification libraries and environments, but generally without the context of a reuse methodology. As these groups became more sophisticated and sought to exchange and reuse verification IP (VIP), they coalesced on the two IEEE standardized verification languages-1800 SystemVerilog and 1647 e-and moved toward the industry-supported methodologies and libraries built with these languages. With the advent of a single methodology implemented in both languages -- OVM/UVM multi-language -- the discussion has returned to HVL features. But now with the reuse methodology known, a true "apples vs. apples" comparison can be made. Sign up for the webinar to get more details.For more details, see https://www.secure-register.net/cadence/q3_10_webinars_verification