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I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement
about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate
and high value to verification engineers everywhere. My colleagues will be
blogging on many of the details, so let me focus on what I think are the three
biggest announced verification benefits of our Silicon Realization solution and what it means to you.
The biggest story is the expansion
of our metric-driven verification approach. Historically, you have been able to
capture your verification intent with an online verification plan (vPlan) and list the coverage that you
needed to achieve thorough verification of the design. Incisive Enterprise
Simulator (IES) then collected all the various coverage metrics and reported
them back against the plan, allowing you to gauge verification completeness and
determine what's next. We then expanded the notion of metrics to include both coverage
and checks (such as assertions), thereby evolving coverage-driven verification into
MDV. The expansion announced yesterday is even broader.
You can now collect metrics from
formal analysis with Incisive Formal Verifier (IFV) and Incisive Enterprise
Verifier (IEV) and combine them with IES results in the report against the
vPlan. This helps you to answer a very common question about how to balance
simulation and formal for fastest convergence to your verification goals. We also have special metrics for
low-power designs and for mixed-signal designs, so that you can plan for these
aspects of the verification process. Of course, we still have tight links to our
SoC Realization and System Realization solutions, including metrics on protocol
compliance from our Verification IP (VIP), metrics from accelerated simulation on
our Palladium platform, and metrics from embedded software running in simulation
The second big news is support for
the emerging Universal Verification Methodology (UVM) standard. As a very
active member of the Accellera committee developing the UVM, we have been involved
in every step of the process. We have kept pace with the methodology and
library as they have evolved, and when UVM 1.0 is released by Accellera within the
next month or so you will be able to hit the ground running. We have added
many features to our simulator to support the UVM, including faster runtime performance and UVM-aware debugging. We want you to have the best UVM experience with
The third major leg of yesterday's announcement is performance. As much as we love to talk about MDV, the UVM and
other advanced topics, in the end you still want us to run our engines as fast
as possible. Last year we introduced the Incisive Advanced Option to provide you
multi-core capabilities and other performance features in IES; we now have the
Specman Advanced Option to provide performance features to our Specman
customers. We are constantly working to enhance compile and runtime performance
for both simulation and formal analysis, focusing on real designs and
testbenches provided by you and other customers.
Finally, let me stress that there is
nothing theoretical or futuristic in this announcement. The many features
described, including my three favorite benefits just discussed, are all
available now with the 10.2 release of Incisive products. So please download
the latest software and refer to my colleagues' blog posts and the product
documentation for lots more information on what's new. We're eager to help you
realize your most complex SoC designs in silicon and to verify them thoroughly
So what do you think Silicon
Realization means for verification engineers?
The truth is out there...sometimes
it's in a blog.