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Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who directs the company's R&D efforts in formal verification -- spoke with Industry Insights columnist Richard Goering. In a wide ranging interview they discussed formal verification usage trends, benefits, roadblocks, appropriate coverage metrics, and the growing alignment of simulation and formal to speed Silicon Realization.
In this video Alok goes a few steps further and declares things like, "the term ‘hybrid' has become obsolete"; and goes on to describe how Formal can drastically simplify the jobs of "Integrators" driving SoC Realization. Bottom-line: if you haven't read the book, you can see the action-packed movie now!
If the video doesn't play, click here.
Question: are you seeing the similar trends in designer, expert, and mixed formal and simulation usage in your company/clients? Please share your thoughts below, or contact me offline.
Happy bug hunting!
Joe Hupcey III
Twitter: @jhupcey, http://twitter.com/jhupcey
Excellent vedio on formal verification insights. Is there a way that this can be shared on other EDA blogging websites?
Another point I wanted to add is that there are "still" companies especially startup semicon/design industries which have not started using Formal verification. It is in those companies , Formal should reach out to. For them insights and experiences how "only formal" can solve the designer's problem of verification will give a boost to formal.
-- Anu Bohra