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Allow us to shamelessly promote a free webinar (including a live demo) this Thursday May 12 at 10am-11am Pacific time, entitled "Verification 1-2-3 with Assertion-Driven Simulation". In a nutshell, in this webinar Solutions Architect Chris Komar and Product Management Director Joe Hupcey III of Team Verify will show a new approach using both formal and dynamic simulation technologies to increase bug detection and produce much clearer RTL, while simultaneously keeping a lid on costs/schedule. Here is the registration link: http://www.secure-register.net/cadence.php?product=203
Some more background, at the risk of spoiling the suspense:
The flow starts with built-in RTL linting and the formal analysis of automatically extracted checks. Next, we transition to one the most effective ways to debug a design: good ol' waveforms. However, we will not use a traditional designer-created testbench, as they typically produce low coverage (hence low bug detection), are a lot of work to write, and they typically cannot be reused. Instead, we will show how you can automagically create stimulus based on reusable SVA or PSL assertions; a process we call "assertion-driven simulation." In short, assertion-driven simulation enables you to simulate, visualize, and debug your code very quickly at low cost.
Even better: we'll go on to show how to use the same exact SVA or PSL environment for formal analysis, which of course can find additional corner-case bugs very quickly. Later on, the assertions can also be reused in the larger verification environment.
Last but not least, we show how you can simultaneously collect coverage from both the formal runs and the assertion-driven simulation. This provides a way to track progress and enables signoff on the formal effort in terms of simulation metrics, and asses its impact on overall verification closure. To prove to you that all this is possible, Chris will give a live demo.
Bottom-line: in one hour we'll show how this new, straightforward "bring-up" methodology increases bug detection and produces much cleaner RTL -- all without a traditional testbench.
Again, registration is free (but a Cadence Community login/registration is required):http://www.secure-register.net/cadence.php?product=203
Hope to see you on the radio this Thursday!
On Twitter: http://twitter.com/teamverify, @teamverify
P.S. If you attended CDNLive EMEA in Munich last week, and you followed the Functional Verification track, you had the opportunity to hear a much more in-depth description of this methodology live from Team Verify's own Kawe Fotouhi.
Kawe's talk covered a lot of ground, so even if you saw his presentation and demo last week by all means join us again for this webinar to refresh your notes.
P.P.S. This webinar is part of an ongoing series that covers topics like Low Power verification, the Specman Advanced Option, metric-driven verification, migrating from VMM to UVM, and more. The complete list of webinars and their respective agendas is listed here:
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