Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Last week teammate Adam Sherer and I had the honor of representing the Incisive functional verification platform at the annual CDNLive for Europe, the Middle East and Africa (EMEA) in Munich, Germany. Among our tasks was to deliver the annual verification roadmap update; support numerous techtorials, demos, and papers; and of course meet with customers and partners. Along the way I couldn't resist taking a few pictures of the event: click here or on the image below to go jump to the annotated gallery.
In addition to the events shown in the gallery, below are some particular highlights of special significance.
Philippe Magarshack keynote
A lot of the energy around EDA360 comes from the support of "apps" via system-level design and verification. However, in his example-packed keynote address, STMicroelectronics' Group VP Philippe Magarshack unapologetically reminded everyone that innovative solutions at the transistor level -- i.e. Silicon Realization in the literal sense of the term -- can enable substantial differentiation (and profitability) all the way up to the Angry Birds software layer.
Several cases in point revolved around low power. After describing a clever, on-chip decoupling capacitor schema that enables a 250 Mhz higher clock frequency for the same power, Magarshack spoke of a new "Adaptive Voltage Scaling" (AVS) technique. With AVS, the chip literally characterizes itself as being "slow", "typical", or "fast". "Slow" chips inform the power control software to boost the supply voltage in order to keep the performance constant. Conversely, "fast" chips let the firmware know the supply voltage can be lowered. Bottom-line: with this self-knowledge, some chips can see power savings of up to 20% vs. the baseline.
One additional point that struck me: unlike the IBM speaker back at ARM Techcon in November, Magarshack's talk was more positive on the ability of silicon to carry the day down to 15 nm when new physical structures like FinFETs are employed.
System Development Suite launch
Returning back up to the System Realization level, the launch of the System Development Suite -- including the Virtual System Platform and the Rapid Prototyping Platform -- was a real highlight of the conference. However, it also had a personal resonance as well. You see, in a past life I was very active in the FPGA prototype and reconfigurable hardware field. Suffice to say the Rapid Prototyping Platform has all the specs that anyone working in this field in the 90's could only dream about. Fast forward to the present, and in my opinion it comes onto today's market as a clear leader right out of the gate.
Even better, the Rapid Prototyping Platform isn't just some slick point tool. Instead, with the ability to exchange databases with Palladium XP, the compatibility with the Incisive verification tools, and the interoperability with the Virtual System Platform, the whole enchilada nicely supports the time-tested "V" development model. In this flow, the Virtual System Platform enables upfront architectural exploration and design and verification, then the Incisive verification platform kicks in for more detailed RTL-level design and verification, and then you go back "up" the far side of the "V" to successively higher levels of verification abstraction enabled by the Rapid Prototyping Platform and Palladium XP.
Incisive functional verification roadmap presentation
A professional highlight was the honor of introducing the 2011 and 2012 functional verification product line roadmaps with my colleague Adam Sherer. As part of this agenda, we also had the opportunity to update our "Trailblazers" on something we've been incubating for a few years now. This included a detailed report on real world experience with this technology in the wild from one of our "lighthouse" users. When followed by a R&D update on more specific innovations we're delivering, it was very satisfying and energizing to see these particular EDA360 deliverables gain the confidence of long-time customers.
Meetings and other re-connections
On a personal note, it was great to reconnect with users I've known since Verisity days. Specifically, my first business trip with the company was to a wintery Munich in February 2003 only a month after I'd signed-on to be the product manager of "Specman Elite." At CDNLive I had the pleasure of reconnecting with several customers and colleagues alike that I met way back during that first trip. I'm also not alone in this renewal process: seeing the camaraderie evident in the attendees' interactions, I dare say that for many CDNLive is much more than a generic networking event.Until next year, may your power consumption be low and your throughput be high!
Joe Hupcey III
Twitter: @jhupcey, http://twitter.com/jhupcey
Image gallery of the event
2011 CDNLive EMEA final program
Introduction to the Cadence System Development Suite